Home › Companies › Jobsbridge1 › ASIC Engineer
ASIC Engineer
Jobsbridge1 · San Jose, CA, United States · Active · SmartRecruiters
Job facts
| Field | Value |
|---|---|
| Company | Jobsbridge1 |
| Title | ASIC Engineer |
| Normalized title | - |
| Department / team | Information Technology |
| Location | San Jose, CA, United States |
| Work model | - |
| Employment type | Contract |
| Salary | - |
| Status | active |
| ATS provider | SmartRecruiters |
| Posted / first seen | 2016-12-08 / 2026-05-31 |
| Changed / last seen | 2026-05-31 / 2026-06-06 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from Jobsbridge1. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through SmartRecruiters. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| City jobs | Active postings in San Jose. | Open |
| Department jobs | Active postings in Information Technology. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | Jobsbridge1 |
| Source | e0da8be9-045c-4774-ab99-9ad3549d53d0 |
| ATS provider | SmartRecruiters |
Description
Ideavat provides I.T staffing solutions, enabling companies & jobseekers engage successfully.
With over 20 man years of contingent staffing experience, the management & execution team is committed to provide customized staffing solutions to employers/hiring managers, helping them identify key talents. Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data/Hadoop developers & architects…& more) remains our primary focus!
Job Title: ASIC Engineer
Location: San Jose, CA
Duration: 6 Months
Minimum Required Skills:
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)
Description:
Should have 2-5 years of experience in FPGA/ASIC Development
Build RTL designs of digital circuits using VHDL and System Verilog
Perform frontend design development and integration of large ASIC designs
Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.
Write design documents including high level interface descriptions and design descriptions.
Write function test cases and test benches to verify functionality of designs
Team work and proactive sharing of knowledge
Comfortable working in a fast paced environment.
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)
All your information will be kept confidential according to EEO guidelines.
Full job record
| Job ID | ff3cd8ca2e8725bfa86eabbee594091cbd08cd06 |
| Org ID | 0775b0a3-9b16-444f-a455-df6216f7629b |
| Source ID | e0da8be9-045c-4774-ab99-9ad3549d53d0 |
| Board ID | e0da8be9-045c-4774-ab99-9ad3549d53d0 |
| Provider | smartrecruiters |
| Provider Job Key | 103587813 |
| Title | ASIC Engineer |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | San Jose, CA, United States |
| Department | Information Technology |
| Team | — |
| Employment Type | contract |
| Workplace Type | — |
| Remote Policy | — |
| Country | United States |
| Region | CA |
| City | San Jose |
| Salary Raw | Ideavat provides I.T staffing solutions, enabling companies & jobseekers engage successfully. With over 20 man years of contingent staffing experience, the management & execution team is committed to provide customized staffing solutions to employers/hiring managers, helping them identify key talents. Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data/Hadoop developers & architects…& more) remains our primary focus! Job Title: ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills: ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) Description: Should have 2-5 years of experience in FPGA/ASIC Development Build RTL designs of digital circuits using VHDL and System Verilog Perform frontend design development and integration of large ASIC designs Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success. Write design documents including high level interface descriptions and design descriptions. Write function test cases and test benches to verify functionality of designs Team work and proactive sharing of knowledge Comfortable working in a fast paced environment. ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) All your information will be kept confidential according to EEO guidelines. |
| Salary Min | — |
| Salary Max | — |
| Salary Currency | — |
| Salary Period | — |
| Source URL | https://jobs.smartrecruiters.com/Jobsbridge1/103587813-asic-engineer |
| Apply URL | https://jobs.smartrecruiters.com/Jobsbridge1/103587813-asic-engineer?oga=true |
| First Seen At | 2026-05-31 17:47:46Z |
| Last Seen At | 2026-06-06 11:07:22Z |
| Last Checked At | 2026-06-06 11:07:22Z |
| Last Changed At | 2026-05-31 17:47:46Z |
| Inactive At | — |
| Source Posted At | 2016-12-08 13:04:18Z |
| Source Updated At | — |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=smartrecruiters/board=jobsbridge1/date=2026-06-06/2026-06-06T11-06-47-945Z-a29dd2012375f4ada13dd74f49a8a26b7ce9dd55aede9a11123a2ee8a8cf4f06.json |
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