Home › Companies › Zealogicsllc › (Sr.) FPGA Design Engineer - Fully Remote(WFH)
(Sr.) FPGA Design Engineer - Fully Remote(WFH)
Zealogicsllc · Remote · Active · JazzHR / ApplyToJob
Job facts
| Field | Value |
|---|---|
| Company | Zealogicsllc |
| Title | (Sr.) FPGA Design Engineer - Fully Remote(WFH) |
| Normalized title | - |
| Department / team | - |
| Location | - |
| Work model | Remote / Remote |
| Employment type | - |
| Salary | - |
| Status | active |
| ATS provider | JazzHR / ApplyToJob |
| Posted / first seen | — / 2026-05-30 |
| Changed / last seen | 2026-05-30 / 2026-06-06 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from Zealogicsllc. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through JazzHR / ApplyToJob. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| Work model jobs | Active Remote postings. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | Zealogicsllc |
| Source | a0143f5c-eca1-4564-b522-fa6107650f3c |
| ATS provider | JazzHR / ApplyToJob |
Description
We are multinational team to collaborate with Fortune 500 client !
You will work with the team in US(Taiwan Working Hours & Reporting Manager can speak Mandarin) and allow to fully Work From Home.
Requirements:
• B.S. in Computer Science, Electrical Engineering or related field
• 5+ years of experience in relevant field
• Strong FPGA design and verification background
• Must have good proficiency in VHDL (good to have some proficiency in Verilog)
• Must have experience in Intel FPGA and corresponding tool chain
• Nice to have experience in JESD204B
• Nice to have knowledge of communication protocols (SPI, I2C, rs232)
• Experience with test-driven design
Core Responsibilities
• Develop communication module
• Develop data stream transmission through JESD204B
• Develop test pattern for SW verification
• Develop DWG function
• Design, develop, and maintain digital logic verification testbenches
• Create and review test plan documents
• Contribute to requirements specifications
• Participate in module- and system-level design reviews
Full job record
| Job ID | fd47a6ef980100fe60dfdc24d76982c92d52ce05 |
| Org ID | 9e15eb95-ecd1-48cc-a563-657594cc1675 |
| Source ID | a0143f5c-eca1-4564-b522-fa6107650f3c |
| Board ID | a0143f5c-eca1-4564-b522-fa6107650f3c |
| Provider | jazzhr |
| Provider Job Key | ylGqa89HSo |
| Title | (Sr.) FPGA Design Engineer - Fully Remote(WFH) |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | — |
| Department | — |
| Team | — |
| Employment Type | — |
| Workplace Type | remote |
| Remote Policy | remote |
| Country | — |
| Region | — |
| City | — |
| Salary Raw | — |
| Salary Min | — |
| Salary Max | — |
| Salary Currency | — |
| Salary Period | — |
| Source URL | https://zealogicsllc.applytojob.com/apply/ylGqa89HSo/Sr-FPGA-Design-Engineer-Fully-RemoteWFH |
| Apply URL | https://zealogicsllc.applytojob.com/apply/ylGqa89HSo/Sr-FPGA-Design-Engineer-Fully-RemoteWFH |
| First Seen At | 2026-05-30 06:02:14Z |
| Last Seen At | 2026-06-06 10:45:58Z |
| Last Checked At | 2026-06-06 10:45:58Z |
| Last Changed At | 2026-05-30 06:02:14Z |
| Inactive At | — |
| Source Posted At | — |
| Source Updated At | — |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=jazzhr/board=zealogicsllc/date=2026-06-06/2026-06-06T10-45-55-913Z-6f908417ee89b4271aaa49634ea56794dbc0059ace265cc959cb3fa090252490.json |
Event Fields
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