Advanced R&D Analog Design Engin - 2 openings

{
  "content_hash": "196e67d83e74671e21f97c6edfc42fe203acb71ce83ff5a8245e0e03b546f4c7",
  "source_hash": "7b1e667c39ecfdfc89b83733bf23a92c461feefe644bfc41e6cf2738b125ba49",
  "last_changed_at": "2026-05-30T05:51:22.377Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "Saint-Sulpice, 1025, Switzerland",
    "city": "Saint-Sulpice",
    "region": null,
    "country": null,
    "is_remote": false,
    "confidence": 0.8
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-06T10:29:40.027Z",
  "launch_scope": {
    "reason": "bamboohr_production_catalog",
    "included": true,
    "location": {
      "raw": "Saint-Sulpice, 1025, Switzerland",
      "city": "Saint-Sulpice",
      "region": null,
      "country": null,
      "is_remote": false,
      "confidence": 0.8
    },
    "countries": []
  },
  "remote_policy": null,
  "salary_period": null,
  "workplace_type": null,
  "salary_currency": null
}

{}

{
  "list_job": {
    "id": "296",
    "isRemote": null,
    "location": {
      "city": "Saint-Sulpice",
      "state": null
    },
    "atsLocation": {
      "city": null,
      "state": null,
      "country": null,
      "province": null
    },
    "departmentId": null,
    "locationType": "2",
    "jobOpeningName": "Advanced R&D Analog Design Engin - 2 openings",
    "departmentLabel": null,
    "employmentStatusLabel": "100%"
  },
  "detail_errors": [],
  "detail_job_opening": {
    "location": {
      "city": "Saint-Sulpice",
      "state": null,
      "postalCode": "1025",
      "addressCountry": "Switzerland"
    },
    "datePosted": "2025-05-05",
    "atsLocation": {
      "city": null,
      "state": null,
      "country": null,
      "countryId": null
    },
    "description": "<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">At<span> </span><span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to<span> </span><span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO)<span> </span></span>of hardware systems — a critical barrier to scalable adoption.</span></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology<span> </span></span>powers a<span> </span><span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric<span> </span></span>that is both<span> </span><span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution<span> </span><span style=\"font-weight: bold\">reduces power consumption significantly<span> </span></span>while preserving<span> </span><span style=\"font-weight: bold\">high bandwidth and ultra-low latency<span> </span></span>— unlocking unprecedented efficiency for AI training and inference at scale.</span><br></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift<span> </span></span>in how AI hardware is built for the future.</span><br></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Job Title:<span> Analog Design Engineer (Advanced Research and Development Department) </span></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Job Location: Switzerland</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-weight: bold\"><span style=\"color: rgb(29, 34, 40)\">Key responsibilities</span></span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Develop block level specifications and models for target designs</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Develop, model, design, and verify performance of custom analog circuits in advanced technology nodes</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Layout design and development, including floor-planning, guiding layout engineers, and post-layout verification</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Design verification at different levels (pre- and post-layout, variation-aware)</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Support and collaborate with the design team, including other design and layout engineers, architects and chip level integration engineers, modeling and system level designers.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Support for post-silicon lab bring-up, debug, characterization and productization.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Produce reports (progress report, analysis, design, modeling, and verification reports)</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Participate in developing concept level architectures and circuits</span></li>\n</ul>\n<p><span style=\"color: rgb(29, 34, 40); font-family: arial, helvetica, sans-serif; font-size: 12pt\"> </span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-weight: bold\"><span style=\"color: rgb(29, 34, 40)\">Skills</span></span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Deep understanding on design and layout techniques for high-speed and high-precision circuits, problem solver, and excellent analytical skills.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experience in developing testbenches and simulation setups to analyze performance of target circuits and systems.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Skillful in layout techniques, such as matching, parasitic estimation and reduction, and deep-submicron related issues.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Advanced user of EDA tool for design and verification, preferably Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction and modelling, EM and IR drop tools, and ESD analysis, among others.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Self-motivated, with strong sense of ownership and responsibility.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Manage workload, schedules and report to internal management and technical teams.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Excellent communication and reporting skills.</span></li>\n</ul>\n<p><span style=\"color: rgb(29, 34, 40); font-family: arial, helvetica, sans-serif; font-size: 12pt\"> </span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-weight: bold\"><span style=\"color: rgb(29, 34, 40)\">Experience</span></span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">5+ years of experience in design and layout of analog and mixed-signal circuits, especially high-speed and high-precision circuits. Examples are: multi-gigabit serial data-link transceivers, RF circuits, equalizers, clock generators, PLLs, clock and data recovery circuits, data converters (ADC or DAC), biasing and bandgap circuits.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">MSc or PhD in electronics/electrical engineering (equivalent or higher).</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experienced with modern semiconductor process technologies, such as CMOS 28nm, and FinFET 16/14nm, 7nm.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experienced in high-level modelling, top-level simulations, and signal integrity.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Solid background on Signal Processing and Communications</span></li>\n</ul>\n<p><span style=\"color: rgb(29, 34, 40); font-family: arial, helvetica, sans-serif; font-size: 12pt\"> </span></p>\n<p><span style=\"color: rgb(29, 34, 40); font-family: arial, helvetica, sans-serif; font-size: 12pt\">If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !</span></p>",
    "compensation": null,
    "departmentId": null,
    "locationType": "2",
    "seekPromoted": false,
    "jobCategoryId": null,
    "jobOpeningName": "Advanced R&D Analog Design Engin - 2 openings",
    "departmentLabel": "",
    "jobOpeningStatus": "Open",
    "minimumExperience": "Experienced",
    "jobOpeningShareUrl": "https://kandou.bamboohr.com/careers/296",
    "employmentStatusLabel": "100%"
  }
}