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HomeCompaniesTaaraconnectPrincipal Analog/Mixed-Signal ASIC Engineer

Principal Analog/Mixed-Signal ASIC Engineer

Taaraconnect · Sunnyvale, CA · Hybrid · Active · $258,000–$294,000 / year · Ashby

Job facts

FieldValue
CompanyTaaraconnect
TitlePrincipal Analog/Mixed-Signal ASIC Engineer
Normalized title-
Department / teamEngineering / Engineering
LocationSunnyvale, CA, United States
Work modelHybrid / Hybrid
Employment typeFull Time
Salary$258,000–$294,000 / year
Statusactive
ATS providerAshby
Posted / first seen / 2026-06-04
Changed / last seen2026-06-04 / 2026-06-18

Related slices

PageWhat it containsOpen
Company jobsActive postings from Taaraconnect.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Ashby.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Sunnyvale.Open
Department jobsActive postings in Engineering.Open
Work model jobsActive Hybrid postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyTaaraconnect
Sourcee27125b8-fae8-4fbe-b822-c91459a83ede
ATS providerAshby

Description

About the Team Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of people who lack abundant and affordable internet by pioneering high-throughput, long-range free-space optical communication (FSOC). Our links use eye-safe lasers propagating between two terminals to transmit high-speed data wirelessly. Lead the charge in bringing our groundbreaking wireless optical communication to the world. Join us to light the way toward bridging the digital divide and illuminating the future. About the Role Taara is seeking a Principal Analog/Mixed-Signal ASIC Engineer to work on the next generation of co-integrated electronic and photonic modules. You will be part of an R&D team developing cutting-edge wireless optical communication systems based on integrated optical phased arrays. The successful candidate will lead ASIC tape-out efforts, own the ASIC top-level architecture, and drive the delivery and validation of ASIC dies. This includes making hands-on contributions to Analog/Mixed-Signal (AMS) ASIC designs and coordinating a small team of ASIC design and layout engineers. The role requires extensive experience in ASIC design and layout—including top-level ownership of ASIC tape-outs at leading commercial foundries—and deep expertise in either or both of these two categories: high-precision AMS circuits and high-speed wireline/silicon photonics interface circuits. We are looking for a highly motivated individual who thrives in ambiguity, enjoys working in a small, dynamic team environment, and has a passion for solving challenging problems that lead to high-impact technological advances. How You Will Make a 10x Impact Own and deliver custom ASICs for co-integration with large-scale photonic integrated circuits to form record-breaking integrated modules. Contribute to ASIC design and layout, system-level optimization, and product strategy. Demonstrate a strong motivation to make the world a better place through technology and a desire to be part of the team making this happen. What You Should Have Ph.D. in Electrical Engineering or a related field. 10 or more years of relevant industry experience with demonstrated achievements in analog/mixed-signal circuit design and implementation in modern CMOS technologies. Demonstrated deep design expertise in one or both of the following categories: High-precision designs: Analog-to-digital and digital-to-analog converters, bandgap references, voltage regulators, amplifiers, and other supporting circuitry. Integration and co-simulation of analog and digital circuits in the context of mixed-signal design and verification. High-speed designs: Front-end circuits for optical communication, including modulator drivers and transimpedance amplifiers (TIAs) operating at tens of GHz, and broadband circuits for serial links including receivers, transmitters, and equalizers. Electromagnetic design of high-frequency transmission lines, inductors, and other passive elements. Experience owning top-level ASIC architecture and coordinating engineering teams. Hands-on experience leading multiple ASIC tape-outs at commercial foundries. Hands-on experience with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Power Integrity (PI), and Signal Integrity (SI) verification. It Would Be Great If You Also Had Experience with planning and executing verification of large Systems-on-Chip (SoCs) incorporating complex digital logic and large numbers of custom-designed blocks. Experience with hardware description languages, such as Register-Transfer Level (RTL) code, and RTL-to-GDS design flows using industry-standard EDA tools for synthesis, timing analysis, and place-and-route. Experience with versioning tools such as SOS and Git. Experience with commercial layout verification software (Calibre or equivalent). Excellent communication and presentation skills, with the ability to work effectively with senior external partners. Hands-on experience advancing a product from the prototype phase to the final production stage. Location & Compensation A hybrid or onsite setup in Sunnyvale, CA, is preferred, though remote work can be considered. Relocation assistance can be provided. The US salary range for this full-time position is $258,000 - $294,000 (inclusive of bonus at target) + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your location during the hiring process.

Full job record

Job IDf430ce9cbb5455aa1bf4d02ab9eb45872d526488
Org ID12660a54-a130-4e94-be35-4adf196ff923
Source IDe27125b8-fae8-4fbe-b822-c91459a83ede
Board IDe27125b8-fae8-4fbe-b822-c91459a83ede
Providerashby
Provider Job Keyfccb8f13-2170-401a-8034-70a477dd8220
TitlePrincipal Analog/Mixed-Signal ASIC Engineer
Normalized Title
Statusactive
Activeyes
Location TextSunnyvale, CA
DepartmentEngineering
TeamEngineering
Employment Typefull_time
Workplace Typehybrid
Remote Policyhybrid
CountryUnited States
RegionCA
CitySunnyvale
Salary Rawsalary range for this full-time position is $258,000 - $294,000 (inclusive of bonus at target) + equity + benefits
Salary Min258,000
Salary Max294,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://jobs.ashbyhq.com/taaraconnect/fccb8f13-2170-401a-8034-70a477dd8220
Apply URLhttps://jobs.ashbyhq.com/taaraconnect/fccb8f13-2170-401a-8034-70a477dd8220/application
First Seen At2026-06-04 13:34:53Z
Last Seen At2026-06-18 10:30:29Z
Last Checked At2026-06-18 10:30:29Z
Last Changed At2026-06-04 13:34:53Z
Inactive At
Source Posted At
Source Updated At
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=ashby/board=taaraconnect/date=2026-06-18/2026-06-18T10-30-11-188Z-9ef036693502d67a24bd7161aa41018cf27d1d3135eeea47347b4f6289db859a.json
Event Fields
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Extensions
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Native Structured
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