Digital Design Engineer, UK, CH

{
  "content_hash": "5a2a2ee5ceeabfbc40e14ecf1a63573fae58c877b09b198f2ab0b263ec0d952a",
  "source_hash": "108234095cb3ab8f4285d4d954bfd25e53aa063cba52263ee7a1bd5e1a2d6cad",
  "last_changed_at": "2026-06-04T11:37:42.154Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "Reading, Berkshire, RG26UB, United Kingdom",
    "city": "Reading",
    "region": "Berkshire",
    "country": null,
    "is_remote": false,
    "confidence": 0.8
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-06T10:29:40.052Z",
  "launch_scope": {
    "reason": "bamboohr_production_catalog",
    "included": true,
    "location": {
      "raw": "Reading, Berkshire, RG26UB, United Kingdom",
      "city": "Reading",
      "region": "Berkshire",
      "country": null,
      "is_remote": false,
      "confidence": 0.8
    },
    "countries": []
  },
  "remote_policy": null,
  "salary_period": null,
  "workplace_type": null,
  "salary_currency": null
}

{}

{
  "list_job": {
    "id": "371",
    "isRemote": null,
    "location": {
      "city": "Reading",
      "state": "Berkshire"
    },
    "atsLocation": {
      "city": null,
      "state": null,
      "country": null,
      "province": null
    },
    "departmentId": "18326",
    "locationType": "2",
    "jobOpeningName": "Digital Design Engineer, UK, CH",
    "departmentLabel": "Engineering",
    "employmentStatusLabel": "100%"
  },
  "detail_errors": [],
  "detail_job_opening": {
    "location": {
      "city": "Reading",
      "state": "Berkshire",
      "postalCode": "RG26UB",
      "addressCountry": "United Kingdom"
    },
    "datePosted": "2026-05-08",
    "atsLocation": {
      "city": null,
      "state": null,
      "country": null,
      "countryId": null
    },
    "description": "<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">At <span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to <span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO) </span>of hardware systems — a critical barrier to scalable adoption.</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology </span>powers a <span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric </span>that is both <span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution <span style=\"font-weight: bold\">reduces power consumption significantly </span>while preserving <span style=\"font-weight: bold\">high bandwidth and ultra-low latency </span>— unlocking unprecedented efficiency for AI training and inference at scale.</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift </span>in how AI hardware is built for the future.</span></p>\n<p><br><br></p>\n<p><span style=\"font-weight: bold\"><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">We are actively seeking for a Digital Design Engineer</span></span></p>\n<p><span style=\"font-weight: bold\"><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Location: L</span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">ausanne (St-Sulpice), Switzerland</span></span></p>\n<p><br><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Responsibility</span></span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Concept definition, analog to digital interface specification</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">RTL design with basics of Dft and IP verification</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Logic synthesis, Timing analysis – desired</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Close interaction with Verification engineers, Analog/Mixed signal designers</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Develop block level specifications of very high-speed digital circuits that meet key performance targets based on system level requirement</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Design and verification of very high-speed digital circuits</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Support for post-silicon lab bring-up, debug, characterization and productization</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Analysis and understanding of high-speed serial protocols (e.g., USB4, PCIe)</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Analog/digital interface specification in close cooperation with analog/mixed-signal designers</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Validation and bring-up of chips in the lab</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Close interaction with verification and physical implementation engineers to verify circuit functionality and compliance with area, timing, and power requirements</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Support and interact with customers on requirements, design specifications, performance results and product delivery</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Support IP and chip level integration</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Manage workload and schedules and report to internal management team and external customers</span></li>\n</ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><br></span><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Required Experience</span></span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">5-10 years’ experience in digital design of key circuits in multi-Gigabit serial data-link transceivers, DDR and low power high performance modern memory interfaces and experience in the semiconductor industry</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Strong technical background in design of high-speed digital circuits in deep-submicron CMOS technologies</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Proven experience in complex digital design and verification of data processing systems</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Proven experience in design and verification of complex regulation systems (configuration, calibration, and dynamic adaption)</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experience in industry standard design EDA tools for design, simulation, and verification</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experience in digital high-speed blocks, CMOS High Speed interface competence would be a preference</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Exposure to the Cadence toolset</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experience with multi-Gigabit serial data transceivers is highly desirable</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experience with analog/digital control interfaces is valuable</span></li>\n</ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><br></span><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Required Skills</span></span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Strong interest in the design of digital circuits and blocks for multi-Gigabit serial ana parallel data-link transceivers, DDR and low power high performance memory and communication interfaces</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Strong scripting and tool setup skill</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Strong analytical skills to translate system-level requirements into design</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">RTL coding skills, CDC and Linting knowledge</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Understanding of verification tools and methodologies is an advantage</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Knowledge of synthesis, STA and signal processing techniques is an advantage</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Advanced knowledge of high-speed and low-power design techniques and high-speed serial protocols</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Scripting (Python preferred) and tool setup skills</span></li>\n</ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><br></span><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Required Education</span></span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Proven experience and/or Masters or Ph.D. in E.E., Communications or other relevant fields</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><br>MSc in electronics/electrical engineering (equivalent or higher)</span><br></li>\n</ul>\n<p><br><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><a href=\"https://kandou.ai/\" target=\"_blank\" rel=\"noopener noreferrer\">https://kandou.ai/</a></span><br></p>\n<p><br></p>",
    "compensation": null,
    "departmentId": "18326",
    "locationType": "2",
    "seekPromoted": false,
    "jobCategoryId": null,
    "jobOpeningName": "Digital Design Engineer, UK, CH",
    "departmentLabel": "Engineering",
    "jobOpeningStatus": "Open",
    "minimumExperience": "Experienced",
    "jobOpeningShareUrl": "https://kandou.bamboohr.com/careers/371",
    "employmentStatusLabel": "100%"
  }
}