Packet Processor Architect

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      "role": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Position Overview</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11.25pt;white-space:pre-wrap;\">We are looking for a highly experienced Packet Processor Architect&nbsp;to lead the definition and implementation of Eridu's industry leading Networking ASIC. This is a unique opportunity to help shape the future of AI Networking.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Responsibilities&nbsp;</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Define and architect packet processing pipelines</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;including related lookup tables and metadata structures for high-performance networking ASICs, including ingress/egress processing, switching/bridging and routing, hash tables and memory lookups, classification, ACL, various tunneling protocols like VxLAN, GRE, IPinIP, QoS, scheduling, traffic management, and congestion control.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Collaborate with the chip and system microarchitects to align the packet processor architecture with system-level goals for throughput, latency, programmability, and power efficiency.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Lead modeling and feasibility analysis of packet flow behavior across L2/L3/L4 layers to validate architectural choices, including throughput, latency, power and area efficiencies.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Drive architectural decisions involving classification, table and lookup optimizations, resource allocation and scalability.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Work closely with RTL, Verification, Firmware, and Physical Design teams to ensure seamless design implementation and handoff.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Guide integration of internal and external IPs (e.g., TCAM, MAC, PCIe, SerDes, DMA) into the broader packet architecture.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Participate in design reviews, performance modeling, Test and Verification strategies and architectural trade-off analysis. </span><span style=\"color:windowtext;white-space:pre-wrap;\">Provide support for various networking protocols and standards related to packet processing</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Contribute to post-silicon validation and tuning of packet flows for performance and correctness. </span><span style=\"color:windowtext;white-space:pre-wrap;\">Investigate and resolve complex issues related to packet processing, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Define architecture-level development methodologies and influence cross-functional design best practices.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Qualifications</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">MSEE or equivalent with </span><b><strong style=\"white-space:pre-wrap;\">15+ years of experience</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;in networking or data-path ASIC architecture and design.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Proven success in </span><b><strong style=\"white-space:pre-wrap;\">architecting packet-processing engines</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;in high-throughput ASICs or SoCs. Experience in designing hash functions, hash tables and lookup engine optimizations.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Familiarity with programmable pipelines, parser/deparser logic, and hardware scheduling engines.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Solid experience working across the ASIC development lifecycle, from concept through productization.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience in high-speed I/O integration&nbsp;(e.g., PCIe Gen5/Gen6, UCIe, SerDes, DMA engines) is a plus.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Understanding of physical design implications on packet architecture (e.g., timing, area, power).</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues</span><span style=\"white-space:pre-wrap;\">. Exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:15pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"color:black;font-size:18pt;white-space:pre-wrap;\">Why Join Us?</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;white-space:pre-wrap;\">At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;white-space:pre-wrap;\">The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:14pt;white-space:pre-wrap;\">Notice to Recruiting Agencies</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.</span></p>",
      "company": "<meta><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"color:black;white-space:pre-wrap;\">About Eridu</strong></b></h4><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver </span><i><em style=\"font-size:11pt;white-space:pre-wrap;\">Faster AI</em></i><span style=\"font-size:11pt;white-space:pre-wrap;\">. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">The company’s solutions and value proposition have been widely validated by leading hyperscalers.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Visit our website </span><a href=\"https://eridu.ai\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(30,74,169);cursor:pointer;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">eridu.ai </span></a><span style=\"font-size:11pt;white-space:pre-wrap;\">to learn more.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:left;\"><br></p>"
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