Senior Principal Validation Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: As a Senior Principal Validation Engineer , you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets. You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction. This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production. Key Responsibilities: Design, develop, and execute validation plans. Own end‑to‑end post‑silicon characterization and validation strategies, translating product requirements into measurable test objectives, pass/fail criteria, and schedules. Drive design reviews and specification alignment. Participate in architecture and design‑spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets. Lead hands‑on test execution and bring‑up. Perform silicon bring‑up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time‑to‑data. Build and maintain automation frameworks. Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed‑signal test benches. Debug and optimize system performance. Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs. Root‑cause cross‑domain failures. Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system‑level tests; coordinate with design, package, and firmware teams to implement fixes. Collaborate with cross‑functional teams. Work closely with mixed‑signal design, firmware, system engineering, and manufacturing to deliver detailed results, root‑cause analyses, optimization recommendations, and formal validation/compliance reports. Document findings and improve methodologies. Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base. Develop test software and platform integrations. Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites. Measure and communicate impact. Define key validation metrics, track coverage and defect trends, and present data‑driven conclusions to stakeholders to influence product direction and release decisions. Basic Qualifications Education — Bachelor of Science in Electrical Engineering required; Master’s degree preferred to demonstrate advanced technical depth and specialization. Experience — At least ten years of hands‑on experience in mixed‑signal, high‑speed lab environments, executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real‑time oscilloscopes, sampling scopes, TDRs, and VNAs. Software Skills — Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction. Retimer Expertise — Practical experience bringing up and debugging retimers, including equalization tuning, pass‑through operation, clocking strategies, and reset and link sequencing. High‑Speed Signaling Knowledge — Deep understanding of NRZ and PAM4 architectures and the ability to investigate jitter sources, CDR and PLL behavior, equalization techniques such as DFE, CTLE, and FFE, as well as crosstalk and power integrity issues. Post‑Silicon Validation — Proven track record in post‑silicon validation and bring‑up of high‑speed PHYs or retimers, with experience developing characterization flows and validating silicon against specifications. Circuit Block Familiarity — Solid working knowledge of key high‑speed building blocks including PLLs, CTLE, DFE, transmitter equalization, and PAM4 signaling fundamentals. Analytical Problem Solving — Exceptional troubleshooting skills with the ability to isolate and narrow complex, multi‑layer failures across analog, digital, firmware, and package domains. Communication — Excellent written and verbal communication skills for clear documentation of findings, presentation of root cause analyses, and collaboration with cross‑functional teams. Preferred Experience: Mixed‑signal system testing and validation — Demonstrated experience in end‑to‑end mixed‑signal system testing, characterization, validation, and compliance activities, including developing test plans, executing characterization flows, and producing formal compliance reports. Signal integrity instrumentation and techniques — Hands‑on proficiency with signal integrity test equipment and methodologies, including BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, and advanced probing techniques for channel and package analysis. Ethernet standards familiarity — Working knowledge of IEEE 802.3 family standards and practical experience validating Ethernet PHYs, link training, autonegotiation, and compliance testing across relevant speeds and media types. Serial protocol expertise — Practical understanding of common serial interfaces such as I2C, I3C, SPI, UART, and other control/status buses used for device bring‑up, firmware interaction, and system integration. Cross‑discipline collaboration — Proven ability to translate SI/PI simulation results into testable lab plans, collaborate with design and firmware teams to close the loop on issues, and document findings that drive design or process improvements. Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly. The base salary range is USD 205,00 - USD 255,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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