Principal Engineer – Wafer Fabrication

{
  "content_hash": "9a8597b0cc857756bce1c2ae577284f6289b1602bba5bf8605de8f64b9d9f8a1",
  "source_hash": "9ca2f4b6cd9f7736704b00a5f285d97de3daa4964206915d2aa5ddc33a3465fc",
  "last_changed_at": "2026-05-31T18:14:26.156Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "United States",
    "city": null,
    "region": null,
    "country": "United States",
    "is_remote": false,
    "confidence": 0.8
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-06T11:52:07.804Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en",
    "location": {
      "raw": "United States",
      "city": null,
      "region": null,
      "country": "United States",
      "is_remote": false,
      "confidence": 0.8
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": null,
  "workplace_type": "on_site",
  "salary_currency": null
}

{}

{
  "detail": {
    "Id": "34556",
    "Title": "Principal Engineer – Wafer Fabrication",
    "media": [],
    "skills": [],
    "JobType": "Experienced",
    "Category": "Direct Production",
    "JobGrade": null,
    "JobLevel": null,
    "JobShift": null,
    "WorkDays": null,
    "WorkHours": null,
    "WorkYears": null,
    "Department": null,
    "HotJobFlag": false,
    "StudyLevel": "Bachelor’s degree",
    "WorkMonths": null,
    "WorkerType": null,
    "GeographyId": 300000000480126,
    "JobFamilyId": 300000009357785,
    "JobFunction": "Manufacturing Engr Mgmt",
    "JobSchedule": "Full time",
    "BusinessUnit": null,
    "ContractType": null,
    "Organization": null,
    "TrendingFlag": false,
    "workLocation": [
      {
        "Country": "US",
        "Region1": null,
        "Region2": "California",
        "Region3": null,
        "Building": null,
        "Latitude": "37.4023",
        "Longitude": "-122.00764",
        "LocationId": 300000764022944,
        "PostalCode": "94089-1005",
        "TownOrCity": "Sunnyvale",
        "AddressLine1": "1322 Bordeaux Drive",
        "AddressLine2": null,
        "AddressLine3": null,
        "AddressLine4": null,
        "LocationName": "Infinera Bordeaux Dr"
      }
    ],
    "ContentLocale": "en",
    "HiringManager": null,
    "LegalEmployer": null,
    "RequisitionId": 300001850215490,
    "WorkplaceType": "On-site",
    "BusinessUnitId": 300000006664259,
    "OrganizationId": 300000806573851,
    "GeographyNodeId": 100002145190048,
    "JobFunctionCode": "MEM",
    "LegalEmployerId": 300001149319675,
    "PrimaryLocation": "United States",
    "RequisitionType": "Standard (Internal & External)",
    "NumberOfOpenings": null,
    "WorkplaceTypeCode": "ORA_ON_SITE",
    "BeFirstToApplyFlag": false,
    "otherWorkLocations": [],
    "secondaryLocations": [],
    "ExternalContactName": null,
    "ShortDescriptionStr": "Senior Manager – Photo-lithography\n\n\tLithography process engineering for Nokia’s compound semiconductor wafer fab.  Focus areas include process sustaining for the 24x7 operation, development, qualification, and release of improved photo-lithography processes on both existing and new technology generations.",
    "ExternalContactEmail": null,
    "ExternalPostedEndDate": null,
    "OtherRequisitionTitle": null,
    "requisitionFlexFields": [
      {
        "Value": "No",
        "Prompt": "Will NSA/CAPS approval be required? (E.g., accessing a US Customer Network?)",
        "ControlType": "SingleChoiceList",
        "SequenceNumber": 5
      },
      {
        "Value": "Individual contributor",
        "Prompt": "Role Type",
        "ControlType": null,
        "SequenceNumber": 8
      },
      {
        "Value": "Yes",
        "Prompt": "Laptop - support with ordering needed",
        "ControlType": "SingleChoiceList",
        "SequenceNumber": 10
      },
      {
        "Value": "US Salary range:  $130,017.39 - \t $241,460.87",
        "Prompt": "US/Canada Salary Range",
        "ControlType": "TextArea",
        "SequenceNumber": 12
      },
      {
        "Value": "Experienced",
        "Prompt": "Experience level",
        "ControlType": "SingleChoiceList",
        "SequenceNumber": 22
      }
    ],
    "ApplyWhenNotPostedFlag": false,
    "DomesticTravelRequired": null,
    "ExternalDescriptionStr": "<p>Team leadership for photolithography process engineering. &nbsp;Focus areas include process sustaining for the 24x7 operation, development, qualification, and release of improved photo-lithography processes on both existing and new technology generations.</p><p>Support the execution of a steep wafer volume and yield roadmap in the existing manufacturing wafer fab (Fab1).</p><p>Team leadership related to process qualification and implementation in a new fab focusing on larger wafer sizes (Fab2).</p><p>Participate in various cross functional teams as a technical content expert.<br>&nbsp;</p>",
    "ObjectVerNumberProfile": null,
    "PrimaryLocationCountry": "US",
    "CorporateDescriptionStr": "<div>\n <b>Advancing connectivity to secure a brighter world.</b>\n</div>\n<div>\n <p><span style=\"box-sizing: border-box;\">Nokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world.&nbsp;</span></p>\n</div>\n<div>\n <a href=\"https://www.nokia.com/careers/life-at-nokia/\" target=\"_blank\" rel=\"nofollow\">Learn more about life at Nokia</a>.\n</div>\n<div style=\"\">\n <br/>\n</div>\n<div style=\"\">\n <br/>\n</div>\n<div style=\"\">\n <p style=\"\"><b>Our recruitment process</b></p>\n <p style=\"\">We act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.</p>\n <p style=\"\">If you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.</p>\n <p style=\"\">The length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates.&nbsp;<a href=\"https://www.nokia.com/careers/#recruitment-process\" target=\"_blank\" rel=\"nofollow\" style=\"\">Discover more about the recruitment process at Nokia</a>.&nbsp;</p>\n</div>",
    "ExternalPostedStartDate": "2026-04-14T23:59:26+00:00",
    "ExternalQualificationsStr": "<ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">JMP, DOE, SPC</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Working knowledge of semiconductor fabrication processes, and specific expertise in photo-lithography.&nbsp;&nbsp;</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Strong leadership and communication skills.&nbsp;</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume.&nbsp;</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Experience supporting&nbsp;a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution.</span></span></p></li></ul></li></ul></li></ul><p><br><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;line-height:107%;padding:0cm;\" lang=\"EN\"><strong>Education/Experience Required:</strong>&nbsp; BS with 5 years’ experience, or MS with 3 years’&nbsp;experience.&nbsp;</span></span></p>",
    "InternalQualificationsStr": "<ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">JMP, DOE, SPC</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Working knowledge of semiconductor fabrication processes, and specific expertise in photo-lithography.&nbsp;&nbsp;</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Strong leadership and communication skills.&nbsp;</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume.&nbsp;</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Experience supporting&nbsp;a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution.</span></span></p></li></ul></li></ul></li></ul><p><br><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;line-height:107%;padding:0cm;\" lang=\"EN\"><strong>Education/Experience Required:</strong>&nbsp; BS with 5 years’ experience, or MS with 3 years’&nbsp;experience.&nbsp;</span></span></p>",
    "OrganizationDescriptionStr": "<div style=\"\">\n Some of our benefits in&nbsp;<a href=\"https://www.nokia.com/careers/our-locations/united-states/\" target=\"_blank\" rel=\"nofollow\" style=\"\">US</a>:\n</div>\n<div style=\"\">\n <ul>\n  <li>Corporate Retirement Savings Plan</li>\n  <li>Health and dental benefits</li>\n  <li>Short-term disability, and long-term disability</li>\n  <li>Life insurance, and AD&amp;D – Company paid 2x base pay</li>\n  <li>Optional or Supplemental life and AD&amp;D insurance (Employee/Spouse/Child)</li>\n  <li>Paid time off for holidays and Vacation</li>\n  <li>Employee Stock Purchase Plan</li>\n  <li>Tuition Assistance Plan</li>\n  <li>Adoption assistance</li>\n  <li>Employee Assistance Program/Work Life Resource Program</li>\n </ul>\n</div>\n<div style=\"\">\n <br/>\n</div>\n<div style=\"\">\n The above benefits exclude students.\n</div>\n<div style=\"\">\n <br/>\n</div>\n<div style=\"\">\n <br/>\n</div>\n<div style=\"\">\n <b>Disclaimer for US/Canada</b>\n</div>\n<div style=\"\">\n <br/>\n</div>\n<div style=\"\">\n Nokia Maintains broad annual base salary ranges for its roles in order to account for variations in knowledge, skills, experience and market conditions, and with consideration to internal peer equity.&nbsp;Check the salary ranges in the job info section for this role.\n</div>\n<div style=\"\">\n <br/>\n</div>\n<div style=\"\">\n <b>All North America job posts will post for a minimum of 7 calendar days and up to 180 days or until candidate/s identified.</b>\n</div>",
    "primaryLocationCoordinates": [
      {
        "Latitude": "39.82844",
        "Longitude": "-98.57939",
        "CountryCode": "US",
        "GeographyId": 300000000480126,
        "GeographyNodeId": 100002145190048
      }
    ],
    "ExternalResponsibilitiesStr": "<ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Optimize coat, exposure and develop processes related to Indium Phosphide (InP) based Photonic Integrated Circuit (PIC) wafer fabrication.&nbsp; Develop and implement processes with improved process capability in both Fab1 and Fab2.</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Develop and deploy control plans to keep photo-lithography processes operating within performance parameters.&nbsp;&nbsp;</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Troubleshoot photo-lithography process problems and drive details of improvement project execution to enable a smooth flow of production and development wafers.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Execute process development and lithography roadmap activities needed for future PIC technology.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Participate in various cross functional teams consisting of equipment, process, and integration engineers to improve process capability, wafer yields, simplify procedures and processes, and release new tools and processes with improved capacity and capability.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Maximize the opportunity to adopt semiconductor industry best practices for Fab2 including automation of wafer and reticle handling and releasing more modern manufacturing tools for PIC wafers with variable topography.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Lead team members partnering with the PIC R&amp;D team to enable the development and qualification of new processes required to deliver next generation high-performance multi-Tb PICs.</span></span></p></li></ul></li></ul></li></ul>",
    "InternalResponsibilitiesStr": "<ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Optimize coat, exposure and develop processes related to Indium Phosphide (InP) based Photonic Integrated Circuit (PIC) wafer fabrication.&nbsp; Develop and implement processes with improved process capability in both Fab1 and Fab2.</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Develop and deploy control plans to keep photo-lithography processes operating within performance parameters.&nbsp;&nbsp;</span></span></p><ul style=\"list-style-type:square;\"><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Troubleshoot photo-lithography process problems and drive details of improvement project execution to enable a smooth flow of production and development wafers.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Execute process development and lithography roadmap activities needed for future PIC technology.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Participate in various cross functional teams consisting of equipment, process, and integration engineers to improve process capability, wafer yields, simplify procedures and processes, and release new tools and processes with improved capacity and capability.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Maximize the opportunity to adopt semiconductor industry best practices for Fab2 including automation of wafer and reticle handling and releasing more modern manufacturing tools for PIC wafers with variable topography.</span></span></p></li><li><p style=\"line-height:normal;tab-stops:list 108.0pt;vertical-align:baseline;\"><span style=\"color:#4A4A4A;font-family:&quot;Times New Roman&quot;,serif;\"><span style=\"border:none windowtext 1.0pt;font-size:12.0pt;padding:0cm;\" lang=\"EN\">Lead team members partnering with the PIC R&amp;D team to enable the development and qualification of new processes required to deliver next generation high-performance multi-Tb PICs.</span></span></p></li></ul></li></ul></li></ul>",
    "InternationalTravelRequired": null
  },
  "list_job": {
    "Id": "34556",
    "Title": "Principal Engineer – Wafer Fabrication",
    "JobType": null,
    "Distance": 1776124800000,
    "JobShift": null,
    "Language": "US",
    "WorkDays": null,
    "JobFamily": null,
    "Relevancy": 2,
    "WorkHours": null,
    "Department": null,
    "HotJobFlag": false,
    "PostedDate": "2026-04-14",
    "StudyLevel": null,
    "WorkerType": null,
    "GeographyId": 300000000480126,
    "JobFunction": null,
    "JobSchedule": null,
    "BusinessUnit": null,
    "ContractType": null,
    "ManagerLevel": null,
    "Organization": null,
    "TrendingFlag": false,
    "workLocation": [
      {
        "Country": "US",
        "Region1": null,
        "Region2": "California",
        "Region3": null,
        "Building": null,
        "Latitude": 37.4023,
        "Longitude": -122.00764,
        "LocationId": 300000764022944,
        "PostalCode": "94089-1005",
        "TownOrCity": "Sunnyvale",
        "AddressLine1": "1322 Bordeaux Drive",
        "AddressLine2": null,
        "AddressLine3": null,
        "AddressLine4": null,
        "LocationName": "Infinera Bordeaux Dr"
      }
    ],
    "LegalEmployer": null,
    "MediaThumbURL": null,
    "WorkplaceType": "On-site",
    "BusinessUnitId": 300000006664259,
    "OrganizationId": 300000806573851,
    "PostingEndDate": null,
    "LegalEmployerId": 300001149319675,
    "PrimaryLocation": "United States",
    "WorkDurationYears": null,
    "WorkplaceTypeCode": "ORA_ON_SITE",
    "BeFirstToApplyFlag": false,
    "WorkDurationMonths": null,
    "otherWorkLocations": [],
    "secondaryLocations": [],
    "ShortDescriptionStr": "Senior Manager – Photo-lithography\n\n\tLithography process engineering for Nokia’s compound semiconductor wafer fab.  Focus areas include process sustaining for the 24x7 operation, development, qualification, and release of improved photo-lithography processes on both existing and new technology generations.",
    "requisitionFlexFields": [],
    "DomesticTravelRequired": null,
    "PrimaryLocationCountry": "US",
    "ExternalQualificationsStr": null,
    "ExternalResponsibilitiesStr": null,
    "InternationalTravelRequired": null
  },
  "detail_meta": {
    "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmRestApi/resources/latest/recruitingCEJobRequisitionDetails?expand=all&onlyData=true&finder=ById;Id=%2234556%22,siteNumber=CX_1",
    "http_status": 200,
    "content_type": "application/json",
    "response_bytes": 19201
  },
  "detail_errors": []
}