Senior DFT Engineer

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex digital SoC designs for 5G, IoT, and LEO satellite communications applications. You will ensure robust testability and quality of our silicon from early design stages through manufacturing tests. This is a full time, exempt position, based out of our Saratoga office.  The target base pay for this position is $120,000 - $220,000 annually.  The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Why E-Space is right for you: As a member of our team, you will play a crucial role in driving our success.  Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals.  In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry. We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space: • An opportunity to really make a difference • Sustainability at our core • Fair and honest workplace • Innovative thinking is encouraged • Competitive salaries • Continuous learning and development • Health and wellness care options • Financial solutions for the future • Optional legal services (US only) • Paid holidays • Paid time off WHAT YOU WILL BE DOING: • Define and implement end-to-end DFT architecture and strategy for complex SoC designs, including scan, MBIST, BIST, and JTAG/IEEE 1149.x • Insert and verify scan chains, compression logic, and test wrappers using industry-standard DFT tools • Own the full ATPG lifecycle: verification, coverage analysis, pattern generation, and ATE bring-up • Perform fault simulation and analyze test coverage metrics to meet manufacturing test requirements • Collaborate with physical design teams to optimize scan chain ordering, routing, and test timing • Define and implement memory BIST (MBIST) and logic BIST (LBIST) strategies for embedded memories • Work with ATE teams to develop test programs and validate tester compatibility • Develop DFT automation scripts and integrate DFT flows into the overall design implementation flow • Perform DFT sign-off verification and resolve DRC/functional issues related to DFT logic • Document DFT specifications, methodology guidelines, and test coverage reports WHAT YOU BRING TO THIS ROLE: • MS/PhD or equivalent experience in Electrical Engineering or a related field • Minimum 8+ years of hands-on experience in Design-for-Test (DFT) for complex digital ASICs or SoCs • Hands-on experience with industry-standard DFT tools such as Synopsys DFT Compiler, Tessent, or equivalent • Strong expertise in scan insertion, ATPG pattern generation (stuck-at, transition, IDDQ), and fault simulation • Experience with compression architectures (EDT, DFTMAX) and advanced DFT techniques • Working knowledge of MBIST architectures and embedded memory test strategies • Familiarity with JTAG/IEEE 1149.1, IEEE 1500, and IEEE 1687 (iJTAG) standards • Proficiency in scripting (Tcl, Python, Perl) for DFT flow automation and analysis • Experience collaborating with physical design and STA teams for scan chain closure • Strong understanding of digital design fundamentals and RTL design practices • Passion for mentoring engineers and scaling technical excellence across a team BONUS POINTS: • Experience with IEEE P1838 (3D-IC test standards) or die-to-die interface test • Exposure to at-speed test methodologies, on-chip clock control for at-speed test, and diagnosis flows for yield improvement • Experience with system-level test and in-system test (IST) approaches • Familiarity with ATE platforms (Advantest, Teradyne) and test program development • Expertise in using programming languages and AI tools for test flow automation • Background in satellite communication, 5G NR, or IoT SoC designs

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      "content": "<p>• MS/PhD or equivalent experience in Electrical Engineering or a related field</p>\n<p>• Minimum 8+ years of hands-on experience in Design-for-Test (DFT) for complex digital ASICs or SoCs</p>\n<p>• Hands-on experience with industry-standard DFT tools such as Synopsys DFT Compiler, Tessent, or equivalent</p>\n<p>• Strong expertise in scan insertion, ATPG pattern generation (stuck-at, transition, IDDQ), and fault simulation</p>\n<p>• Experience with compression architectures (EDT, DFTMAX) and advanced DFT techniques</p>\n<p>• Working knowledge of MBIST architectures and embedded memory test strategies</p>\n<p>• Familiarity with JTAG/IEEE 1149.1, IEEE 1500, and IEEE 1687 (iJTAG) standards</p>\n<p>• Proficiency in scripting (Tcl, Python, Perl) for DFT flow automation and analysis</p>\n<p>• Experience collaborating with physical design and STA teams for scan chain closure</p>\n<p>• Strong understanding of digital design fundamentals and RTL design practices</p>\n<p>• Passion for mentoring engineers and scaling technical excellence across a team</p>"
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