Principal Design Verification Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs. Key Responsibilities Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification. Work with RTL designers to troubleshoot and resolve design issues. Drive verification strategy and methodology for SoCs in server and networking applications. Required Qualifications Bachelor’s degree in Electrical Engineering (Master’s preferred). 8+ years of experience in SoC verification, particularly for server and networking applications. Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle. Proficiency with industry-standard simulators, version control, and regression systems. Strong debugging and coverage analysis skills. Experience developing and executing test sequences, generating stimuli, and identifying verification holes. Familiarity with verification of switching architectures, including packet processing and forwarding engines. Excellent communication skills and ability to work independently with minimal supervision. Preferred Qualifications Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand. Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators. Knowledge of Ethernet/PCIe switching and central buffer architectures. Experience with emulation platforms and hardware-software co-verification Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

{
  "content_hash": "9d9e770e76946c98ff295bdc0ac012e1a74ee0551a5647e8e4cd333bda43aec8",
  "source_hash": "e78939d96ffcbde5d108f20cb6e10654ab1bda33950dc2bf05ffe2ccb3782c62",
  "last_changed_at": "2026-06-06T07:35:38.727Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "San Jose, United States",
    "city": null,
    "region": null,
    "country": "United States",
    "is_remote": false,
    "confidence": 0.95
  },
  "salary_max": 230000,
  "salary_min": 185000,
  "inferred_at": "2026-06-06T07:35:38.666Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en",
    "location": {
      "raw": "San Jose, United States",
      "city": null,
      "region": null,
      "country": "United States",
      "is_remote": false,
      "confidence": 0.95
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": "year",
  "workplace_type": null,
  "salary_currency": "USD"
}

{}

{
  "title": "Principal Design Verification Engineer ",
  "offices": [
    {
      "id": 4000118005,
      "name": "San Jose",
      "location": "San Jose, United States",
      "child_ids": [],
      "parent_id": 4019546005
    }
  ],
  "language": "en",
  "location": {
    "name": "San Jose, United States"
  },
  "metadata": [
    {
      "id": 12122734005,
      "name": "Country",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 12122790005,
      "name": "City",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 7826080005,
      "name": "Job Family/Domain",
      "value": "Design Verification",
      "value_type": "single_select"
    },
    {
      "id": 7826085005,
      "name": "Role Type",
      "value": "Experienced",
      "value_type": "single_select"
    }
  ],
  "updated_at": "2026-06-05T13:07:16-04:00",
  "departments": [
    {
      "id": 4025527005,
      "name": "ASIC Engineering",
      "child_ids": [],
      "parent_id": 4000196005
    }
  ],
  "company_name": "Astera Labs",
  "requisition_id": 4426612005,
  "first_published": "2026-03-26T19:08:39-04:00",
  "application_deadline": null
}