DFM RET Engineer

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    "ExternalDescriptionStr": "<p><strong>Change the world. Love your job.&nbsp;</strong><br>Texas Instruments is in an exciting era of growth and innovation, and our Advanced Technology Development (ATD) organization is at the center of it. We are developing the 28nm process technologies that will define TI’s next generation of analog and embedded processing capabilities. As part of ATD, you won’t just support production, you’ll create the technology that makes it possible. Our engineers are working at the leading edge of computational lithography, Resolution Enhancement Techniques, and advanced process integration, solving the fundamental patterning and process challenges that determine whether a 28nm technology can be manufactured at scale and at yield. The work done in ATD directly enables fabs that will manufacture tens of millions of analog and embedded processing chips every day supporting customer demand for decades to come. We’re committed to responsible, sustainable semiconductor manufacturing and to building a diverse, technically excellent team that drives meaningful impact across the industry. In this role, you’ll work at the intersection of fundamental research and high-volume manufacturing, turning process innovations into production-ready technologies that power electronics everywhere.</p><p><span><strong>Job Description:</strong></span></p><p>At 28nm and below, photolithography cannot simply print a chip design as drawn but rather optical diffraction causes critical features to print incorrectly, with direct consequences to yield and device performance. Solving that problem is your job. As a DFM/OPC Engineer in TI’s Resolution Enhancement Techniques (RET) team within ATD, you are the technical authority responsible for bridging the gap between what designers draw and what the fab can reliably print. You’ll develop, optimize, and deploy Optical Proximity Correction (OPC) models and Design for Manufacturability (DFM) solutions that ensure every product tapeout can be accurately realized in silicon at 28nm at yield entitlement. This role sits at the intersection of computational lithography, layout design, and process integration; your work is a prerequisite for every analog product TI ships from LFAB.</p><p><span><strong>Responsibilities:</strong></span></p><ul style=\"padding-left: 48px;\"><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Develop, evaluate, and implement advanced OPC models and recipes for 28nm and equivalent advanced node technologies</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Perform comprehensive DFM analysis on product designs, identifying and mitigating potential manufacturing issues (e.g., hotspots, yield detractors)</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Collaborate with design teams to define DFM guidelines and ensure layout compliance with manufacturing capabilities</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance, yield, and process window</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Interface with OPC and lithography engineers to co-optimize layout structures for printability</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Analyze lithography process data and wafer yield data to identify root causes of patterning defects and drive corrective actions</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Evaluate and qualify new OPC/DFM software tools and methodologies</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Develop and maintain automation scripts for OPC/DFM flows</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Contribute to DFM-aware layout methodologies for custom analog IPs</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Mentor junior engineers and contribute to team knowledge sharing</p></li></ul>",
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    "CorporateDescriptionStr": "<div>\n <div>\n  <b>Why TI?</b>\n </div>\n <div>\n  <ul>\n   <li>Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.</li>\n   <li>We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours.&nbsp;<a href=\"https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/pages/4012\" target=\"_blank\" rel=\"nofollow\">Meet the people of TI</a></li>\n   <li>Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us.</li>\n  </ul>\n </div>\n <div>\n  <br>\n </div>\n <div>\n  <div></div>\n  <div>\n   <b>About Texas Instruments</b>\n  </div>\n  <div>\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more&nbsp;at&nbsp;<a href=\"https://www.ti.com/\" target=\"_blank\" rel=\"nofollow\">TI.com</a>.\n  </div>\n  <div>\n   <br>\n  </div>\n  <div>\n   <div>\n    Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.\n   </div>\n   <div>\n    <br>\n   </div>\n   <div>\n    If you are interested in this position, please apply to this requisition.\n   </div>\n  </div>\n </div>\n</div>\n<div>\n</div>",
    "ExternalPostedStartDate": "2026-03-23T17:19:06+00:00",
    "ExternalQualificationsStr": "<p><span><strong>Minimum Requirements:</strong></span></p><ul style=\"padding-left: 48px;\"><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Master’s or Ph.D. in Electrical Engineering, Physics, Materials Science, or related field</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">5+ years of hands-on OPC and DFM experience in the semiconductor industry</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Strong understanding of optical lithography principles and RET (OPC, SRA, assist features, mask technology)</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Hands-on experience with industry-standard OPC tools (e.g., Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion)</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Familiarity with 28nm/22nm process constraints and lithographic limitations</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Proficiency in scripting languages (Python, TCL, Perl, or equivalent)</p></li></ul><p>&nbsp;</p><p><span><strong>Preferred Qualifications:</strong></span></p><ul style=\"padding-left: 48px;\"><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Experience with analog layout interaction with lithography and OPC flows</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Familiarity with layout tools (e.g., Cadence Virtuoso); knowledge of DRC and LVS</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Experience applying machine learning or AI techniques to OPC/DFM problems</p></li><li><p style=\"margin-bottom: 4pt; margin-right: 0in; margin-top: 0in;\">Strong cross-functional collaboration and analytical skills</p></li></ul>",
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