Home › Companies › Eridu › ASIC Validation Engineer
ASIC Validation Engineer
Eridu · Saratoga, CA, United States · On Site · Active · $185,000–$250,000 / year · Rippling ATS
Job facts
| Field | Value |
|---|---|
| Company | Eridu |
| Title | ASIC Validation Engineer |
| Normalized title | - |
| Department / team | ASIC Engineering |
| Location | Saratoga, CA, United States |
| Work model | On Site |
| Employment type | Full Time |
| Salary | $185,000–$250,000 / year |
| Status | active |
| ATS provider | Rippling ATS |
| Posted / first seen | 2025-11-17 / 2026-05-29 |
| Changed / last seen | 2026-06-06 / 2026-06-06 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from Eridu. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through Rippling ATS. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| City jobs | Active postings in Saratoga. | Open |
| Department jobs | Active postings in ASIC Engineering. | Open |
| Work model jobs | Active On Site postings. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | Eridu |
| Source | 2e3b3faf-1f18-443b-b03c-ab436c316a6b |
| ATS provider | Rippling ATS |
Description
company
About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
role
Position Overview We are hiring multiple positions from Sr. Engineer to Principal Engineer.
We are looking for a highly experienced Post-Silicon ASIC Validation Engineer with deep expertise in networking ASICs and chiplet-based architectures. You will lead bring-up, validation, and characterization of complex multi-die systems integrating high-speed interconnects such as UCIe, SerDes, PCIe, and Ethernet PHYs. This position offers the opportunity to work on next-generation networking SoCs and disaggregated chiplet platforms, collaborating across architecture, design, firmware, and system teams to ensure first-silicon success and robust product readiness.
Responsibilities Drive post-silicon validation and bring-up of networking ASICs and chiplet-based SoCs. Own validation planning, coverage definition, and test execution across UCIe, SerDes, and networking subsystems. Develop automation and test infrastructure for high-speed link and protocol validation (Python). Perform silicon bring-up, including power sequencing, link training, and PHY initialization. Execute link-level and system-level validation of UCIe interfaces, die-to-die interconnects, and high-bandwidth chiplet fabrics. Debug complex cross-domain issues spanning RTL, firmware, analog PHY, and package-level interactions. Characterize signal integrity, latency, throughput, and thermal/power behavior across PVT corners. Collaborate with board design and test engineering teams on validation platforms, sockets, and characterization boards. Qualifications B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. Experience in post-silicon validation and bring-up of complex ASICs or SoCs. Hands-on experience with UCIe, PCIe and high-speed interconnect standards. Proficiency in Python for scripting, automation, and data analysis. Strong lab experience using oscilloscopes, BERTs, logic analyzers, and JTAG-based debuggers. Excellent communication skills and experience working in cross-functional silicon development teams. Preferred Qualifications Experience with chiplet-based systems, UCIe protocol stack validation, and multi-die integration challenges (power delivery, timing, thermal). Familiarity with emulation or FPGA prototyping platforms for pre-silicon validation. Exposure to hardware/software co-validation for networking protocols or control-plane software. Strong knowledge of package-level interactions and signal integrity analysis for high-speed interfaces.
Why Join Us? At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees.
Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
Full job record
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| Provider Job Key | 05add4f2-308f-448c-8873-67ab6ba17f57 |
| Title | ASIC Validation Engineer |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | Saratoga, CA, United States |
| Department | ASIC Engineering |
| Team | — |
| Employment Type | full_time |
| Workplace Type | on_site |
| Remote Policy | — |
| Country | United States |
| Region | CA |
| City | Saratoga |
| Salary Raw | USD 185000-250000 YEAR |
| Salary Min | 185,000 |
| Salary Max | 250,000 |
| Salary Currency | USD |
| Salary Period | year |
| Source URL | https://ats.rippling.com/eridu-ai/jobs/05add4f2-308f-448c-8873-67ab6ba17f57 |
| Apply URL | https://ats.rippling.com/eridu-ai/jobs/05add4f2-308f-448c-8873-67ab6ba17f57 |
| First Seen At | 2026-05-29 07:14:02Z |
| Last Seen At | 2026-06-06 19:44:35Z |
| Last Checked At | 2026-06-06 19:44:35Z |
| Last Changed At | 2026-06-06 19:44:35Z |
| Inactive At | — |
| Source Posted At | 2025-11-17 22:13:19Z |
| Source Updated At | — |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=rippling/board=eridu-ai/date=2026-06-06/2026-06-06T19-44-33-762Z-4b761a1811184974f9facfa7bb3d3a7e8696180848a08b199b5b79a934e7d18e.json |
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"role": "<meta><h1 style=\"font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:1px;margin-top:24px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Position Overview</strong></b></h1><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"white-space:pre-wrap;\">We are hiring multiple positions from Sr. Engineer to Principal Engineer. </strong></b></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:rgb(33,33,33);font-size:11pt;white-space:pre-wrap;\">We are looking for a highly experienced Post-Silicon ASIC Validation Engineer with deep expertise in networking ASICs and chiplet-based architectures. You will lead bring-up, validation, and characterization of complex multi-die systems integrating high-speed interconnects such as UCIe, SerDes, PCIe, and Ethernet PHYs. This position offers the opportunity to work on next-generation networking SoCs and disaggregated chiplet platforms, collaborating across architecture, design, firmware, and system teams to ensure first-silicon success and robust product readiness.</span></p><h1 style=\"font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:1px;margin-top:24px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Responsibilities </strong></b></h1><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Drive post-silicon validation and bring-up of networking ASICs and chiplet-based SoCs.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Own validation planning, coverage definition, and test execution across UCIe, SerDes, and networking subsystems.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Develop automation and test infrastructure for high-speed link and protocol validation (Python).</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Perform silicon bring-up, including power sequencing, link training, and PHY initialization.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Execute link-level and system-level validation of UCIe interfaces, die-to-die interconnects, and high-bandwidth chiplet fabrics.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Debug complex cross-domain issues spanning RTL, firmware, analog PHY, and package-level interactions.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Characterize signal integrity, latency, throughput, and thermal/power behavior across PVT corners.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Collaborate with board design and test engineering teams on validation platforms, sockets, and characterization boards.</span></li></ul><h1 style=\"font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:1px;margin-top:24px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Qualifications</strong></b></h1><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Experience in post-silicon validation and bring-up of complex ASICs or SoCs.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Hands-on experience with UCIe, PCIe and high-speed interconnect standards.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Proficiency in Python for scripting, automation, and data analysis.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Strong lab experience using oscilloscopes, BERTs, logic analyzers, and JTAG-based debuggers.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Excellent communication skills and experience working in cross-functional silicon development teams.</span></li></ul><h1 style=\"font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:1px;margin-top:24px;margin-bottom:4px;text-align:start;padding-left:0px;\"><span style=\"white-space:pre-wrap;\">Preferred Qualifications</span></h1><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Experience with chiplet-based systems, UCIe protocol stack validation, and multi-die integration challenges (power delivery, timing, thermal).</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Familiarity with emulation or FPGA prototyping platforms for pre-silicon validation.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Exposure to hardware/software co-validation for networking protocols or control-plane software.</span></li><li style=\"color:rgb(0,0,0);font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Strong knowledge of package-level interactions and signal integrity analysis for high-speed interfaces.</span></li></ul><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><br></p><h5 style=\"font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0px;margin-top:10px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Why Join Us?</strong></b></h5><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers. </span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\"> </span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. </span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\"> </span></p><h6 style=\"font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Notice to Recruiting Agencies</strong></b></h6><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees.</span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.</span></p>",
"company": "<meta><h1 style=\"font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:1px;margin-top:24px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"color:black;white-space:pre-wrap;\">About Eridu </strong></b></h1><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver </span><i><em style=\"font-size:11pt;white-space:pre-wrap;\">Faster AI</em></i><span style=\"font-size:11pt;white-space:pre-wrap;\">. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.</span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\"> </span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">The company’s solutions and value proposition have been widely validated by leading hyperscalers.</span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\"> </span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.</span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\"> </span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Visit our website </span><a href=\"http://eridu.ai\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(30,74,169);cursor:pointer;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">eridu.ai</span></a><span style=\"font-size:11pt;white-space:pre-wrap;\"> to learn more.</span></p><p style=\"font-family:"Basel Grotesk",Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:left;\"><br></p>"
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