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HomeCompaniesAstera LabsPrincipal Electronics Engineer - Board Validation

Principal Electronics Engineer - Board Validation

Astera Labs · San Jose, CA · Active · $185,000–$230,000 / year · Greenhouse

Job facts

FieldValue
CompanyAstera Labs
TitlePrincipal Electronics Engineer - Board Validation
Normalized title-
Department / teamHardware Engineering
LocationSan Jose, CA, United States
Work model-
Employment type-
Salary$185,000–$230,000 / year
Statusactive
ATS providerGreenhouse
Posted / first seen2025-12-30 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Astera Labs.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Greenhouse.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in San Jose.Open
Department jobsActive postings in Hardware Engineering.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyAstera Labs
Sourced86aa7ea-cb4f-47f9-8c47-6663a3d12412
ATS providerGreenhouse

Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As a Principal Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products. Key Responsibilities: Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out. Develop comprehensive hardware electrical validation plans using correct test methods and processes. Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board. Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc. Rework components on the PCBAs to unblock debugging activities. Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams. Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc. Support the new designs using knowledge of existing products to de-risk new features and requirements. Self-informed of new industry test standards and equipment to introduce modern testing methodologies. Specify test equipment, develop test fixtures, help improve hardware lab functions. Required Skills: Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug Bachelor degree in EE with 10+ years of experience in hardware test or design Define/refine hardware test methodologies and identify appropriate test equipment Expert understanding of design and test for power regulators, PDNs, Bode, clock gens Ability to produce test description from a schematic design, and execute and document results Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc. Automating lab equipment to optimize test processes, Python preferred Preferred Skills: Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc. EMI/EMC compliance Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc. PLM, Arena or equivalent Understanding of the ASIC/silicon product development process Base salary range is $185,000 USD-$230,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Full job record

Job IDdc1f57346400c62b30cc8d65698bc1b949a91e51
Org IDb525b888-3625-40e7-98d3-4e6be9a9695e
Source IDd86aa7ea-cb4f-47f9-8c47-6663a3d12412
Board IDd86aa7ea-cb4f-47f9-8c47-6663a3d12412
Providergreenhouse
Provider Job Key4644664005
TitlePrincipal Electronics Engineer - Board Validation
Normalized Title
Statusactive
Activeyes
Location TextSan Jose, CA
DepartmentHardware Engineering
Team
Employment Type
Workplace Type
Remote Policy
CountryUnited States
RegionCA
CitySan Jose
Salary Rawsalary range is $185,000 USD-$230,000 USD, and will be determined based on the candidate's capabilities
Salary Min185,000
Salary Max230,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://job-boards.greenhouse.io/asteralabs/jobs/4644664005
Apply URLhttps://job-boards.greenhouse.io/asteralabs/jobs/4644664005
First Seen At2026-05-29 22:43:09Z
Last Seen At2026-06-06 07:35:38Z
Last Checked At2026-06-06 07:35:38Z
Last Changed At2026-06-06 07:35:38Z
Inactive At
Source Posted At2025-12-30 22:11:06Z
Source Updated At2026-06-05 17:07:16Z
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=greenhouse/board=asteralabs/date=2026-06-06/2026-06-06T07-35-38-320Z-b9bc00c682f65f8b3d23456e0d78ee7a880569fb19bc97a8c3a658a2e5bcaed5.json
Event Fields
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Parsed Structured
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Extensions
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Native Structured
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