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Senior FPGA Design Engineer

09a14fa2 30e8 49e6 80ed 82a5812bd326 9200365399883 2 · Chandler, AZ, US, Chandler, AZ · On Site · Active · ADP Workforce Now Recruiting

Job facts

FieldValue
Company09a14fa2 30e8 49e6 80ed 82a5812bd326 9200365399883 2
TitleSenior FPGA Design Engineer
Normalized title-
Department / team-
LocationChandler, AZ, United States
Work modelOn Site
Employment typeFull Time
Salary-
Statusactive
ATS providerADP Workforce Now Recruiting
Posted / first seen2026-02-02 / 2026-05-31
Changed / last seen2026-06-06 / 2026-06-06

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Linked records

Company09a14fa2 30e8 49e6 80ed 82a5812bd326 9200365399883 2
Source0ace756a-1450-4b92-ac54-2afac1b4e7bd
ATS providerADP Workforce Now Recruiting

Description

Job Title: Senior FPGA Engineer III Department: Engineering->Platforms->FPGA SoC Group Reports To: Director, Platforms FLSA Status: Exempt Last Modified: 9/10/2025 Level : T3 Location Chandler, AZ – Onsite 5 Days a week Company Overview Comtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world’s most innovative communications solutions. For more information, please visit www.comtech.com . We’re seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you’re invigorated by our mission, values, and drive to change the world — we’d love to have you apply. Position Summary Senior FPGA Designer with experience in the entire design flow for complex FPGA’s. Responsibilities Design, develop, document, debug and test FPGA SoC systems; including: IP Integration into FPGA Projects (synthesis/implementation) High-Performance FPGA IP (VHDL/SystemVerilog) Userspace Drivers for FPGA IP (C++) Firmware for Embedded Microcontrollers (C) Utilize strong communication skills to effectively work and communicate with team members and engineering management. Qualifications Strong digital design engineer with FPGA/ASIC SoC design experience Strong FPGA Implementation with Altera Quartus or Xilinx Vivado Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP Capable of creating RTL simulations to identify and resolve most issues before hardware tests Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC) Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths Experience contributing to schematic capture and layout for FPGA portions of PCB designs Experience implementing at least one Gigabit Transceiver Protocol: PCI Express, Interlaken, USB SuperSpeed 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-4, 100GBASE-R4 Experience implementing Network Protocols, such as: L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G) L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi (Highly Desired) Proficient in SW development with C, C++ and GIT version control Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.) Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams Desired Qualifications Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired) Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTree Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18 Working knowledge of communication networks and security within a zero-trust environment Experience with Partial Reconfiguration/DFX or PCIe CvP Possess an active DoD clearance or demonstrate readiness to obtain one Education Bachelors in Electrical or Computer Engineering (or related degree). Experience : 5+ years of FPGA/ASIC SoC design experience. Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.

Full job record

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First Seen At2026-05-31 18:13:15Z
Last Seen At2026-06-06 12:47:43Z
Last Checked At2026-06-06 12:47:43Z
Last Changed At2026-06-06 12:47:43Z
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    "requisitionDescription": "<div><div><div><div><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><br></span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Job Title:</strong>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;Senior FPGA Engineer III</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Department:</strong>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Engineering-&gt;Platforms-&gt;FPGA SoC Group</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Reports To:</strong>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;Director, Platforms</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>FLSA Status:</strong>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;Exempt</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Last Modified:</strong>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;9/10/2025</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Level</strong>: &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; T3</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Location</strong>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Chandler, AZ &ndash; Onsite 5 Days a week</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>&nbsp;</strong></span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Company Overview</strong></span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\">Comtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world&rsquo;s most innovative communications solutions. For more information, please visit&nbsp;<a href=\"https://cts.businesswire.com/ct/CT?id=smartlink&url=http%3A%2F%2Fwww.comtech.com&esheet=53569004&newsitemid=20231002073328&lan=en-US&anchor=www.comtech.com&index=3&md5=95d01a7b8df70a781b0bf99e20725318\" target=\"_blank\" title=\"https://cts.businesswire.com/ct/ct?id=smartlink&url=http%3a%2f%2fwww.comtech.com&esheet=53569004&newsitemid=20231002073328&lan=en-us&anchor=www.comtech.com&index=3&md5=95d01a7b8df70a781b0bf99e20725318\" style=\"font-family: arial,sans-serif;\">www.comtech.com</a>.&nbsp;<br>&nbsp;&nbsp;<br>We&rsquo;re seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you&rsquo;re invigorated by our mission, values, and drive to change the world &mdash; we&rsquo;d love to have you apply.</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>&nbsp;<br>Position Summary</strong></span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\">Senior FPGA Designer with experience in the entire design flow for complex FPGA&rsquo;s.</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>&nbsp;</strong></span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Responsibilities</strong></span></p><ul style=\"list-style-type: disc;\"><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Design, develop, document, debug and test FPGA SoC systems; including:<ol style=\"list-style-type: circle; font-size: initial; font-family: initial;\"><li style=\"font-size: 14px; font-family: arial, sans-serif;\">IP Integration into FPGA Projects (synthesis/implementation)</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">High-Performance FPGA IP (VHDL/SystemVerilog)</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Userspace Drivers for FPGA IP (C++)</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Firmware for Embedded Microcontrollers (C)</li></ol></li></ul><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in 0in 8pt; font-size: 14px; font-family: arial, sans-serif;\">Utilize strong communication skills to effectively work and communicate with team members and engineering management.</li></ul><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Qualifications</strong></span></p><ul class=\"decimal_type\" style=\"list-style-type: disc;\"><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Strong digital design engineer with FPGA/ASIC SoC design experience</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Strong FPGA Implementation with Altera Quartus or Xilinx Vivado</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Capable of creating RTL simulations to identify and resolve most issues before hardware tests</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Experience contributing to schematic capture and layout for FPGA portions of PCB designs</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Experience implementing at least one Gigabit Transceiver Protocol:<ol style=\"list-style-type: circle; font-size: initial; font-family: initial;\"><li style=\"font-size: 14px; font-family: arial, sans-serif;\">PCI Express, Interlaken, USB SuperSpeed</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">1000BASE-X/SGMII, 10GBASE-R, 40GBASE-4, 100GBASE-R4</li></ol></li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">Experience implementing Network Protocols, such as:<ul class=\"decimal_type\" style=\"font-size: initial; font-family: initial;\"><li style=\"font-size: 14px; font-family: arial, sans-serif;\">L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G)</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP</li><li style=\"font-size: 14px; font-family: arial, sans-serif;\">L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi<br><u>(Highly Desired)</u></li></ul></li></ul><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in 0in 8pt; font-size: 14px; font-family: arial, sans-serif;\">Proficient in SW development with C, C++ and GIT version control</li><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)</li><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams</li></ul><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Desired Qualifications</strong></span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi <u>(Highly Desired)</u></li><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTree</li><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18</li><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Working knowledge of communication networks and security within a zero-trust environment</li><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Experience with Partial Reconfiguration/DFX or PCIe CvP</li><li style=\"margin: 0in; font-size: 14px; font-family: arial, sans-serif;\">Possess an active DoD clearance or demonstrate readiness to obtain one</li></ul><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Education</strong></span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in 0in 8pt; font-size: 14px; font-family: arial, sans-serif;\">Bachelors in Electrical or Computer Engineering (or related degree).</li></ul><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Experience</strong>:</span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in 0in 8pt; font-size: 14px; font-family: arial, sans-serif;\">5+ years of FPGA/ASIC SoC design experience.</li></ul><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:.5in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\">&nbsp;</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><br></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><span style=\"font-size: 14px; font-family: arial, sans-serif;\"><strong>Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.&nbsp;</strong>&nbsp;</span></p></div></div></div></div>\n",
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