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Communications DSP Engineer

Aalyria Technologies, Inc. · Remote (United States), United States · Remote · Active · $185,000–$215,000 / year · Rippling ATS

Job facts

FieldValue
CompanyAalyria Technologies, Inc.
TitleCommunications DSP Engineer
Normalized title-
Department / teamSpace
LocationUnited States
Work modelRemote / Remote
Employment typeFull Time
Salary$185,000–$215,000 / year
Statusactive
ATS providerRippling ATS
Posted / first seen2026-04-23 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

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Linked records

CompanyAalyria Technologies, Inc.
Sourceb96cc765-c456-47ad-ba49-ce552822da8d
ATS providerRippling ATS

Description

company About Aalyria: Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any hardware across land, sea, air, and space. role Role Overview: The Aalyria Space team is seeking a highly skilled DSP Engineer to develop next-generation modem technologies for free space optical communication systems. This role sits at the intersection of advanced digital signal processing, system architecture, and real-world hardware implementation. You will design and optimize DSP algorithms and architectures that enable robust, high-throughput links across challenging channels, helping push beyond current limits in coherent communications. You’ll collaborate closely with cross-functional teams spanning ASIC/FPGA design, RF/optical hardware, and system engineering to translate advanced algorithms into efficient, deployable modem solutions. This is a remote position that will include occasional travel to our Mountain View, CA location. Key Responsibilities: Design, develop, and optimize coherent DSP algorithms for high-speed communication systems Architect end-to-end modem DSP chains including equalization, timing recovery, carrier recovery, and FEC integration. Perform system-level modeling, simulation, and performance analysis, including link budgets and channel impairments. Develop advanced algorithms such as: Adaptive equalization Timing and carrier synchronization loops Impairment mitigation Evaluate and model optical and electrical channels, including optical components, ADC/DAC, AFE, and mixed-signal impairments. Define DSP architecture specifications for ASIC/FPGA implementation, ensuring efficient mapping to hardware. Collaborate with hardware and firmware teams to integrate DSP algorithms into modem designs. Support lab bring-up, validation, and characterization of modem systems. Analyze relevant industry standards (e.g., OIF, Ethernet, optical transport) and incorporate them into designs. Required Qualifications: Active security clearance, or the eligibility to obtain one. M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. Strong foundation in: Digital signal processing Communication theory High-speed communication system design Hands-on experience with coherent DSP or high-speed SerDes/optical systems. Proficiency in MATLAB, Python, and/or C/C++ for modeling and algorithm development. Experience with: Adaptive equalization and synchronization algorithms FEC techniques (e.g., LDPC, Viterbi, soft decoding) System-level simulation and performance analysis Familiarity with ASIC/FPGA implementation flows and hardware constraints. Ability to translate theoretical algorithms into practical, power- and area-efficient implementations. Strong problem-solving skills and ability to work across multidisciplinary teams. Hands-on lab experience with high-speed communication systems. Experience with developing cycle accurate fixed point system models. Preferred Qualifications: Experience with coherent optical communication systems. Knowledge of IMDD or optical transport systems. Experience with time-interleaved ADCs and calibration techniques. Familiarity with industry standards (OIF, OpenROADM, IEEE Ethernet). Exposure to RTL design (VHDL/SystemVerilog) or firmware development. What We Offer: Innovative Environment: Work at a cutting-edge company shaping the future of aerospace communications. Impactful Work: Directly contribute to critical national security programs and initiatives. Growth Opportunities: Expand your career with opportunities for professional development and advancement. Inclusive Culture: Be part of a collaborative, supportive, and inclusive workplace where your contributions matter. Flexibility: Flexible working arrangements including hybrid remote/in-office schedules. Compensation and Equity: Competitive salary, comprehensive benefits (401(k), dental, vision, health, life insurance), paid time off, and equity options. ITAR/EAR Requirements: This position involves access to export-controlled information. To comply with U.S. government export regulations, applicants must meet one of the following criteria: (A) Qualify as a U.S. person, which includes: U.S. citizen or national U.S. lawful permanent resident (green card holder) Refugee under 8 U.S.C. 1157 Asylee under 8 U.S.C. 1158 (B) Be eligible to access export-controlled information without requiring an export authorization. (C) Be eligible and reasonably likely to obtain the necessary export authorization from the appropriate U.S. government agency. The company reserves the right to decline pursuing an export licensing process for legitimate business-related reasons. Equal Opportunity Employer Statement: Aalyria is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We do not discriminate based on race, color, religion, sex (including pregnancy, gender identity, and sexual orientation), national origin, age, disability status, genetic information, protected veteran status, or any other characteristic protected by law. Qualified applicants from all backgrounds are encouraged to apply.

Full job record

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Source IDb96cc765-c456-47ad-ba49-ce552822da8d
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Providerrippling
Provider Job Key861116e5-bc73-4cee-b980-ac0b6677b70c
TitleCommunications DSP Engineer
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Statusactive
Activeyes
Location TextRemote (United States), United States
DepartmentSpace
Team—
Employment Typefull_time
Workplace Typeremote
Remote Policyremote
CountryUnited States
Region—
City—
Salary RawUSD 185000-215000 YEAR
Salary Min185,000
Salary Max215,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://ats.rippling.com/aalyria-careers/jobs/861116e5-bc73-4cee-b980-ac0b6677b70c
Apply URLhttps://ats.rippling.com/aalyria-careers/jobs/861116e5-bc73-4cee-b980-ac0b6677b70c
First Seen At2026-05-29 07:12:01Z
Last Seen At2026-06-06 08:44:31Z
Last Checked At2026-06-06 08:44:31Z
Last Changed At2026-06-06 08:44:31Z
Inactive At—
Source Posted At2026-04-23 18:35:46Z
Source Updated At—
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      "role": "<meta><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Role Overview:</strong></b></h2><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">The Aalyria Space team is seeking a highly skilled DSP Engineer to develop next-generation modem technologies for free space optical communication systems. This role sits at the intersection of advanced digital signal processing, system architecture, and real-world hardware implementation. You will design and optimize DSP algorithms and architectures that enable robust, high-throughput links across challenging channels, helping push beyond current limits in coherent communications. You’ll collaborate closely with cross-functional teams spanning ASIC/FPGA design, RF/optical hardware, and system engineering to translate advanced algorithms into efficient, deployable modem solutions.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">This is a remote position that will include occasional travel to our Mountain View, CA location.</span></p><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Key Responsibilities:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Design, develop, and optimize coherent DSP algorithms for high-speed communication systems</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Architect end-to-end modem DSP chains including equalization, timing recovery, carrier recovery, and FEC integration.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Perform system-level modeling, simulation, and performance analysis, including link budgets and channel impairments.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Develop advanced algorithms such as:</span></li><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Adaptive equalization </span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Timing and carrier synchronization loops</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Impairment mitigation</span></li></ul></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Evaluate and model optical and electrical channels, including optical components, ADC/DAC, AFE, and mixed-signal impairments.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Define DSP architecture specifications for ASIC/FPGA implementation, ensuring efficient mapping to hardware.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Collaborate with hardware and firmware teams to integrate DSP algorithms into modem designs.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Support lab bring-up, validation, and characterization of modem systems.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Analyze relevant industry standards (e.g., OIF, Ethernet, optical transport) and incorporate them into designs.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Required Qualifications:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Active security clearance, or the eligibility to obtain one.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Strong foundation in:</span></li><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Digital signal processing</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Communication theory</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">High-speed communication system design</span></li></ul></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Hands-on experience with coherent DSP or high-speed SerDes/optical systems.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Proficiency in MATLAB, Python, and/or C/C++ for modeling and algorithm development.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with:</span></li><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Adaptive equalization and synchronization algorithms</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">FEC techniques (e.g., LDPC, Viterbi, soft decoding)</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">System-level simulation and performance analysis</span></li></ul></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Familiarity with ASIC/FPGA implementation flows and hardware constraints.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Ability to translate theoretical algorithms into practical, power- and area-efficient implementations.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Strong problem-solving skills and ability to work across multidisciplinary teams.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Hands-on lab experience with high-speed communication systems.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with developing cycle accurate fixed point system models.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Preferred Qualifications:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with coherent optical communication systems.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Knowledge of IMDD or optical transport systems.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with time-interleaved ADCs and calibration techniques.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Familiarity with industry standards (OIF, OpenROADM, IEEE Ethernet).</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Exposure to RTL design (VHDL/SystemVerilog) or firmware development.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">What We Offer:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Innovative Environment: </strong></b><span style=\"white-space:pre-wrap;\">Work at a cutting-edge company shaping the future of aerospace communications.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Impactful Work:</strong></b><span style=\"white-space:pre-wrap;\"> Directly contribute to critical national security programs and initiatives.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Growth Opportunities: </strong></b><span style=\"white-space:pre-wrap;\">Expand your career with opportunities for professional development and advancement.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Inclusive Culture:</strong></b><span style=\"white-space:pre-wrap;\"> Be part of a collaborative, supportive, and inclusive workplace where your contributions matter.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Flexibility: </strong></b><span style=\"white-space:pre-wrap;\">Flexible working arrangements including hybrid remote/in-office schedules.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Compensation and Equity:</strong></b><span style=\"white-space:pre-wrap;\"> Competitive salary, comprehensive benefits (401(k), dental, vision, health, life insurance), paid time off, and equity options.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">ITAR/EAR Requirements:</strong></b></h2><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">This position involves access to export-controlled information. To comply with U.S. government export regulations, applicants must meet one of the following criteria:</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">(A) Qualify as a U.S. person, which includes:</span></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">U.S. citizen or national</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">U.S. lawful permanent resident (green card holder)</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Refugee under 8 U.S.C. 1157</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Asylee under 8 U.S.C. 1158</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">(B) Be eligible to access export-controlled information without requiring an export authorization.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">(C) Be eligible and reasonably likely to obtain the necessary export authorization from the appropriate U.S. government agency.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">The company reserves the right to decline pursuing an export licensing process for legitimate business-related reasons.</span></p><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Equal Opportunity Employer Statement:</strong></b></h2><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">Aalyria is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We do not discriminate based on race, color, religion, sex (including pregnancy, gender identity, and sexual orientation), national origin, age, disability status, genetic information, protected veteran status, or any other characteristic protected by law. Qualified applicants from all backgrounds are encouraged to apply.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p>",
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