Principal Engineer, Physical Design

About InnoPhase IoT If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you’ll find your playground at Innophase IoT. We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT! Overview of Role As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions. Location San Diego or San Jose, CA Responsibilities Complete entire physical implementation of the block and chip level Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV. Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route Implement ECOs for timing closure Signal EM/Noise and Power IR/EM analysis and fix DRC/LVS/ERC/ANTENNA analysis and clean up Timing verification and signoff Physical verification and sign off Minimum Qualifications Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification. The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC Netlist (or RTL)-GDS physical implementation experience In depth knowledge of major EDA tools/design flows Strong Cadence experience/background Experience with TSMC N22 or below technology Experience in chip integration and signoff Experience in Perl/TCL language programming Preferred Qualifications Strong experience in Low-power implementation methodology Strong experience in Advanced timing signoff methodology Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows Able to independently complete Netlist-GDS P&R, signoff task Proven record in multi-million gate design production tapeouts It is key to unleash the potential in every employee, every team, every leader, and the company herself. We know employees perform best when motivated, appreciated and recognized, and can be themselves. We are committed to building a culture where every voice can be heard, everyone has room for growth and can make meaningful contributions. At the end of the day, we want success not just for the company, but also for everyone who believes in the company, the vision, and the future.

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