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HomeCompaniesEtchedPhysical Design Engineer

Physical Design Engineer

Etched · Austin · On Site · Active · Ashby

Job facts

FieldValue
CompanyEtched
TitlePhysical Design Engineer
Normalized title-
Department / teamASIC / ASIC
LocationAustin, TX, United States
Work modelOn Site
Employment typeFull Time
Salary-
Statusactive
ATS providerAshby
Posted / first seen / 2026-05-29
Changed / last seen2026-05-29 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Etched.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Ashby.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Austin.Open
Department jobsActive postings in ASIC.Open
Work model jobsActive On Site postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyEtched
Sourcea291cc81-a8d4-46c4-bb86-2fc3ead775e4
ATS providerAshby

Description

About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is looking for exceptional Physical Design engineers to join our team. In this role, you will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed. Key Responsibilities Deeply understand what is involved in physical design Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure Collaborate with RTL Designers and provide Physical Design feedback to improve PPA Drive dashboards that show the convergence of projects related to PD Optimize tool flows, working with EDA vendors to incorporate the latest features Accountable for block level closure Supervise the outsourcing of physical design to a 3rd party service You may be a good fit if you have 5-10+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on advanced process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.) Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Deeply creative and able to think from first principles Strong candidates may also have experience with Familiarity with transformer models and machine learning Ability to program with Python or another scripting language Familiarity with AI tools for programming/coding Startup experience or comfort working in fast-paced environments Benefits Medical, dental, and vision packages with generous premium coverage $500 per month credit for waiving medical benefits Various wellness benefits covering fitness, mental health, and more Daily lunch + dinner in our office Unlimited compute budget subject to ROI justification How we’re different Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We have a growing presence in Austin and a core team in San Jose (Santana Row), and we greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

Full job record

Job IDc8e4c6167d6f87e53d233b7361d9b6a42dcffd92
Org IDd0883ffa-496c-4a26-8b05-802f34b95e11
Source IDa291cc81-a8d4-46c4-bb86-2fc3ead775e4
Board IDa291cc81-a8d4-46c4-bb86-2fc3ead775e4
Providerashby
Provider Job Keye194099a-b7c0-4aa7-9e6d-06a666de6275
TitlePhysical Design Engineer
Normalized Title
Statusactive
Activeyes
Location TextAustin
DepartmentASIC
TeamASIC
Employment Typefull_time
Workplace Typeon_site
Remote Policy
CountryUnited States
RegionTX
CityAustin
Salary Raw
Salary Min
Salary Max
Salary Currency
Salary Period
Source URLhttps://jobs.ashbyhq.com/Etched/e194099a-b7c0-4aa7-9e6d-06a666de6275
Apply URLhttps://jobs.ashbyhq.com/Etched/e194099a-b7c0-4aa7-9e6d-06a666de6275/application
First Seen At2026-05-29 06:46:25Z
Last Seen At2026-06-06 09:24:43Z
Last Checked At2026-06-06 09:24:43Z
Last Changed At2026-05-29 06:46:25Z
Inactive At
Source Posted At
Source Updated At
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=ashby/board=Etched/date=2026-06-06/2026-06-06T09-23-41-038Z-39bb6bc30ed3a209d5f658994606cf084b0341ec013329649a948ef2f31baa64.json
Event Fields
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Parsed Structured
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Extensions
{}
Native Structured
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