Physical Design Engineers - 2 openings

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    "description": "<p><span style=\"font-family: Inter, sans-serif\">At <span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to <span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO) </span>of hardware systems — a critical barrier to scalable adoption.</span></p>\n<p><br><br></p>\n<p><span style=\"font-family: Inter, sans-serif\">Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology </span>powers a <span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric </span>that is both <span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution <span style=\"font-weight: bold\">reduces power consumption significantly </span>while preserving <span style=\"font-weight: bold\">high bandwidth and ultra-low latency </span>— unlocking unprecedented efficiency for AI training and inference at scale.</span></p>\n<p><br><br></p>\n<p><span style=\"font-family: Inter, sans-serif\">Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift </span>in how AI</span></p>\n<p><span style=\"font-family: Inter, sans-serif\">hardware is built for the future.</span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px\"> </span></p>\n<p><span style=\"font-family: Inter, sans-serif\"><span style=\"font-size: 15px\">We are actively seeking <span style=\"font-weight: bold\">Physical Design Engineers based in Hyderabad OR Bangalore</span></span><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-weight: bold\"><span style=\"color: white\"><br></span></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px; font-weight: bold\">Required competences - Experience</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">10+ years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM and IR drop, ESD, etc.</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Expertise in Timing Constraints and Static Timing Analysis (STA)</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Experience in CPF/UPF technologies and flows is highly desirable</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Exposure to flip-chip package technologies and wire bond package technologies</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Experience in hierarchical floor planning and implementation</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Experience in release management and tape out procedures</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Experience in library setup and flow development with focus on cross project reusability</span></li>\n<li><span style=\"font-family: Inter, sans-serif\"><span style=\"font-size: 15px\">Experience in DFT methodologies and implementation schemes<span style=\"font-weight: bold\"><span style=\"color: white\">Required</span></span></span></span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px\"><span style=\"font-weight: bold\"><span style=\"color: white\">Competencies – Skills</span></span></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px; font-weight: bold\">Required competences - Skills</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Good understanding of RTL to GDS implementation flow (synthesis, P&amp;R, LEC, PV) </span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)</span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px\"> <span style=\"font-weight: bold\"><span style=\"color: white\">Responsibility and Authority</span></span></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px; font-weight: bold\">Responsibility and Authority<br></span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">As a Physical Design Engineer, you will work closely with the Architecture, RTL, DFT teams to ensure first-time-right high-volume silicon production</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Timing constraints improvement and timing constraints validation, signoff Static Timing Analysis and block-level timing closure</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Synthesis, block level floor-planning, power grid design, place &amp; route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Participate in developing improvements to scripts/methodologies/flows</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Interact closely with the design team to understand requirements and implement solutions as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Support IP and chip level integration</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Support and interact with customers on requirements and IP delivery</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Manage workload and schedule and report to internal management team</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px; font-weight: bold\">Education</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 15px\">Bachelors/Masters of Engineering in Electronics and Electrical Engineering/Computer Science (equivalent or higher)</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 15px\"><a href=\"https://www.kandou.ai/\" target=\"_blank\" rel=\"noopener noreferrer\">https://www.kandou.ai/</a></span><br></p>",
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