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FPGA Manager

Kepler · Toronto, Ontario · Hybrid · Active · Lever

Job facts

Field	Value
Company	Kepler
Title	FPGA Manager
Normalized title	-
Department / team	Engineering / FPGA
Location	Toronto, ON, Canada
Work model	Hybrid / Hybrid
Employment type	Full Time Regular
Salary	-
Status	active
ATS provider	Lever
Posted / first seen	2026-04-01 / 2026-05-29
Changed / last seen	2026-05-29 / 2026-06-06

Related slices

Page	What it contains	Open
Company jobs	Active postings from Kepler.	Open
Company breakdowns	Role, location, ATS, and work model facets for this company.	Open
ATS provider jobs	Active postings observed through Lever.	Open
Provider filtered search	The same provider as a filtered job collection.	Open
City jobs	Active postings in Toronto.	Open
Department jobs	Active postings in Engineering.	Open
Work model jobs	Active Hybrid postings.	Open
Lifecycle events	Open, update, close, and reopen events for this posting.	Open
Original posting	Canonical source or apply URL captured from the ATS.	Open

Linked records

Company	Kepler
Source	4cbdc6b6-22d5-49c6-94e8-24b953473ba2
ATS provider	Lever

Description

At Kepler Communications, we're not just imagining the future of on-demand space connectivity - we're leading it! Our mission is to provide real-time Internet access for space-based assets, enabling a new era of data-driven exploration and innovation. With 33 satellites launched to date, Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities. Industry-leading technology is only part of the story. What sets Kepler apart is our team: bold thinkers, skilled builders, and passionate problem-solvers who thrive on pushing the boundaries of what’s possible in space. We believe great ideas come from diverse perspectives, and we’re committed to creating an environment where you can grow, lead, and make a global impact. If you’re ready to reach higher, move faster, and do work that shapes the future space economy - this is your launchpad. Come build the future with Kepler! What We Offer: * Competitive compensation with a robust equity plan to share in our success. * Comprehensive coverage for health, dental, and vision insurance—including dependents. * Unlimited vacation, supportive parental leave policy, and company-wide holiday shutdown. * Semi-annual company-wide parties and frequent in-office team events. * Relocation packages available for approved roles. * $1,500 annual professional development fund to support your growth. * Fully stocked Toronto office kitchen with snacks, drinks, games and top-notch kitchen appliances. * Town Halls, Celebration Calls, and Company-wide events to stay connected and engaged. * We’re a certified Great Place to Work®, five years in a row! Kepler is seeking an experienced FPGA Manager to lead the design, development, and deployment of FPGA-based systems that power Kepler’s satellite payloads and ground infrastructure. You’ll balance leadership, technical oversight, and team development while contributing to the execution of mission-critical programs. You will play a critical role in delivering high-reliability, radiation-tolerant, and performance-optimized digital systems for space applications. Expected Time Breakdown: 50% - Team leadership and execution oversight 25% - Technical guidance and design input 15% - Recruiting and on-boarding 10% - Administrative and reporting Employment Equity & Accommodation Statement Kepler Communications is an equal opportunity employer committed to building a diverse and inclusive workplace. We welcome applications from all qualified individuals, including women, Indigenous peoples, persons with disabilities, members of visible minorities, and people of all sexual orientations and gender identities. If you require accommodation during any stage of the recruitment process, please contact our People & Culture team at [email protected], and we will work with you to meet your needs. Key Responsibilities: Lead, mentor, and maintain a high-performing, geographically diverse FPGA team , fostering a collaborative culture that exemplifies Kepler’s Values Ensure the team has the tools, training, and support needed to deliver high-quality RTL designs Provide ongoing coaching, technical guidance, and career development through regular 1:1s and structured performance reviews Monitor day-to-day execution across multiple projects, ensuring alignment with program goals and timelines Support hiring plans, lead interviews, and onboard new team member Own the FPGA development across the full lifecycle: Architecture, design, verification, bring-up, debugging, and deployment Partner with program and product leads to define scope, resourcing, and delivery milestones Support vendor selection for tools and IP, and guide make/buy decisions Own and drive adoption of the FPGA engineering design process, establishing and championing best practices for RTL design, simulation, verification, and CI/CD Manage project timelines, resource allocation, and long-term technical strategy Required Skills and Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in FPGA/RTL design and development with 3+ years of which were leading or managing engineering teams Track record of building healthy team culture and driving performance through clear expectations and feedback Strong communication skills and the ability to work cross-functionally Proven ability to manage shifting priorities and drive execution through ambiguity via agile development practices Proven ability to deliver complex hardware systems from concept to production Proven ability to collaborate effectively with other teams both within and beyond the Engineering department Strong technical fundamentals in FPGA/RTL design Experience in SystemVerilog/Verilog or VHDL Experience with FPGA toolchains (e.g., Vivado, Quartus, Libero) Background in digital design fundamentals such as timing closure, high-speed interfaces (e.g., SERDES, PCIe, Ethernet), I/O planning, power management Experience with simulation and verification methodologies (e.g., UVM, testbenches, formal verification) and tools (e.g. Questa, VUnit, ALint Pro, Verilator, Verible, GHDL, IcarusVerilog) Bonus Points: Experience with space-grade or radiation-tolerant FPGA design Experience with high-speed data pipelines and networking protocols Background in satellite communications, SDR, or DSP algorithms Familiarity with heterogeneous compute systems (e.g. MPSoC UltraScale+, Versal ACAP) Experience with CI/CD pipelines for FPGA development Knowledge of scripting languages (Python, TCL, Bash) for automation Experience working in fast-paced startup or aerospace environments Familiarity with or certification in automotive/aerospace safety processes/standards Why Kepler?: Work on cutting-edge space infrastructure and satellite technology Be part of a rapidly growing company shaping the future of space communications Collaborate with a highly skilled, mission-driven team Competitive compensation, equity, and benefits Opportunities for growth and leadership in a scaling organization

Full job record

Job ID	c4e8c0b5087db8c5a595947c6466fe33bb9f5730
Org ID	9624f7e8-4711-4180-8000-5e32946b7d42
Source ID	4cbdc6b6-22d5-49c6-94e8-24b953473ba2
Board ID	4cbdc6b6-22d5-49c6-94e8-24b953473ba2
Provider	lever
Provider Job Key	692d580f-1542-4125-befe-4dad6426d01d
Title	FPGA Manager
Normalized Title	—
Status	active
Active	yes
Location Text	Toronto, Ontario
Department	Engineering
Team	FPGA
Employment Type	Full-time Regular
Workplace Type	hybrid
Remote Policy	hybrid
Country	Canada
Region	ON
City	Toronto
Salary Raw	—
Salary Min	—
Salary Max	—
Salary Currency	—
Salary Period	—
Source URL	https://jobs.lever.co/kepler/692d580f-1542-4125-befe-4dad6426d01d
Apply URL	https://jobs.lever.co/kepler/692d580f-1542-4125-befe-4dad6426d01d/apply
First Seen At	2026-05-29 07:00:27Z
Last Seen At	2026-06-06 20:15:59Z
Last Checked At	2026-06-06 20:15:59Z
Last Changed At	2026-05-29 07:00:27Z
Inactive At	—
Source Posted At	2026-04-01 17:54:50Z
Source Updated At	—
Raw Payload Uri	s3://job-postings-prod-raw-590183727216/raw/provider=lever/board=kepler/date=2026-06-06/2026-06-06T20-15-58-267Z-0fc04af64ea2129eff5fcdd59c9261f1ea603076b222f6b6cacda9a33e69995d.json

Event Fields

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Parsed Structured

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Extensions

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Native Structured

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      "text": "Required Skills and Qualifications:",
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experience in FPGA/RTL design and development with <span data-mark-type=\"annotation\" data-mark-annotation-type=\"inlineComment\" data-id=\"7ac81ff7-cfd1-47df-863d-71c322bba697\" data-prosemirror-content-type=\"mark\" data-prosemirror-mark-name=\"annotation\" id=\"7ac81ff7-cfd1-47df-863d-71c322bba697\">3+ years of which were leading or managing engineering teams</span></p>\n</li>\n<li data-local-id=\"d304d38c91a4\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"ca9121b04507\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Track record of building healthy team culture and driving performance through clear expectations and feedback</p>\n</li>\n<li data-local-id=\"91a75d411bcf\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"d09c8755c385\" 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data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"aed97187d9ac\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Proven ability to deliver complex hardware systems from concept to production</p>\n</li>\n<li data-local-id=\"f46f0bce-b496-4cc8-b6ec-74e6f386d12d\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"784d45aee3d6\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Proven ability to collaborate effectively with other teams both within and beyond the Engineering department</p>\n</li>\n<li data-local-id=\"172e5908eabf\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"930440b4b040\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Strong technical fundamentals in FPGA/RTL design</p>\n</li>\n<li data-local-id=\"5fa28d14331b\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"4c7ad814692a\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\"><span data-mark-type=\"annotation\" data-mark-annotation-type=\"inlineComment\" data-id=\"8c1356de-112f-45a5-9d33-541e0f518ee3\" data-prosemirror-content-type=\"mark\" data-prosemirror-mark-name=\"annotation\" id=\"8c1356de-112f-45a5-9d33-541e0f518ee3\">Experience in SystemVerilog/Verilog or VHDL</span></p>\n</li>\n<li data-local-id=\"d26310da9b6e\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"970031ac9f86\" data-prosemirror-content-type=\"node\" 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    },
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      "text": "Bonus Points:",
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    },
    {
      "text": "Why Kepler?:",
      "content": "<div>\n<ul data-local-id=\"e0fdde79-544c-4a27-962c-746706883f5f\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"bulletList\" data-prosemirror-node-block=\"true\" data-pm-slice=\"3 3 []\">\n<li data-local-id=\"039e6229-c13e-4471-af04-dc759826ea06\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"9bfd613fe37e\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Work on cutting-edge space infrastructure and satellite technology</p>\n</li>\n<li data-local-id=\"20a3420e-5804-45a5-a88e-55196655196b\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"85e345f37836\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Be part of a rapidly growing company shaping the future of space communications</p>\n</li>\n<li data-local-id=\"f46c2e02-334a-46f7-bade-f041ce56b123\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"a59603f44a2e\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Collaborate with a highly skilled, mission-driven team</p>\n</li>\n<li data-local-id=\"0bcbdd74-de54-4ea1-8525-eabafaea43e5\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"befa5c13946d\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Competitive compensation, equity, and benefits</p>\n</li>\n<li data-local-id=\"ae51d0ae-f676-44bf-b286-69b4b0be87c3\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"listItem\" data-prosemirror-node-block=\"true\">\n<p data-local-id=\"763d5b679170\" data-prosemirror-content-type=\"node\" data-prosemirror-node-name=\"paragraph\" data-prosemirror-node-block=\"true\">Opportunities for growth and leadership in a scaling organization</p>\n</li>\n\n</ul></div>"
    }
  ],
  "country": "CA",
  "createdAt": 1775066090442,
  "updatedAt": null,
  "categories": {
    "team": "FPGA",
    "location": "Toronto, Ontario",
    "commitment": "Full-time Regular",
    "department": "Engineering",
    "allLocations": [
      "Toronto, Ontario"
    ]
  },
  "salaryRange": null,
  "workplaceType": "hybrid"
}

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