Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)

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    "title": "Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)",
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    "datePosted": "2026-06-08T04:00:00.000Z",
    "description": "<h2>Basic Qualifications </h2>\n<p>Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.</p>\n<p> </p>\n<p><strong>Clearance Requirements:</strong></p>\n<p>Department of Defense TS/SCI security clearance is preferred at time of hire. <strong>Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire.</strong> Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.</p>\n<p> </p>\n<h2>Responsibilities for this Position</h2>\n<p><strong>Duties and Tasks:</strong>• Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments• Determines architecture, system simulation and detailed design approach• Defines module interfaces and all aspects of device design and simulation• Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization• Creates test and simulation plans that establish functional criteria• Verifies test results and analyzes performance• May also review vendor capabilities, foundry technologies, device libraries and simulation tools• Participates in the improvement of the ASIC/FPGA organizational processes• Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle• Contributes to the research and analysis of data, such as customer design proposal specifications, and manuals to determine feasibility of design or application• Selects components and equipment based on analysis of specifications and reliability• May provide leadership and/or direction to lower level employees• Independently determines approach to solutions• Contributes to the completion of major programs and projects• Plans and executes project tasks for activities described above</p>\n<p><strong>Knowledge, Skills and Abilities:</strong>• Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories• Proficient in the principles and techniques of ASIC/FPGA design• Proficient understanding of ASIC/FPGA processes• Proficient knowledge of other related disciplines• Keeps abreast of technology trends• Proficient awareness of business objectives and Engineering’s role in achieving• Proficient in Microsoft Office applications• Proficient in ASIC/FPGA design tools• Proficient written and verbal communications skills • Ability to think creatively • Ability to multi-task • Proficient skill in communicating issues, impacts, and corrective actions • Proficient ability to recognize and clearly report information relevant to sound ASIC/FPGA design • Proficient ability to develop and sell concepts and ideas • Regular contact with senior levels of internal work groups • Works under limited direction • Contact with project leaders and other professionals within the Engineering department and with project teams across the company • Some contact with external customers</p>\n<p>• Identifies opportunities to apply AI for continuous improvement and innovation</p>\n<p> </p>\n<p><strong>Key Responsibilities: </strong></p>\n<p>The individual will be responsible for and participate in the ASIC/FPGA product life cycle (requirements, design, implementation, and test).  Must be knowledgeable in VHDL and/or Verilog RTL coding and be proficient in micro-architecture design.  Successful candidates will have an understanding of digital design concepts and proficient in the digital design tool flow (synthesis, timing, place and route, and in system debug). </p>\n<p> </p>\n<p>This candidate must have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the design goals.  Must have strong written and oral communication skills.</p>\n<p> </p>\n<p><strong>Basic Qualifications for Adv ASIC</strong> <strong>/FPGA Design Engineer:</strong> </p>\n<ul>\n <li>Ability to generate micro architecture and detailed design approaches</li>\n</ul>\n<ul>\n <li>Proficient in async design principals, timing closure, and constraint generation</li>\n</ul>\n<ul>\n <li>Proficiency in HDL (VHDL/Verilog)</li>\n <li>Proficiency in scripting languages such as Tcl, Python, or Perl</li>\n <li>Effective communication, presentation skills, and high proficiency in technical problem solving</li>\n <li>U.S. citizenship with the ability to obtain and maintain a Secret security clearance</li>\n</ul>\n<p><strong>Preferred Qualifications:</strong> </p>\n<ul>\n <li>Leads technical tasks or small projects</li>\n <li>Understanding of high reliability design principals</li>\n <li>Experience with Xilinx and Microchip FPGAs along with associated tools (ISE, Vivado, Libero)</li>\n <li>Experience with synthesis tools (Precision, Synplify)</li>\n <li>Experience with verification tools (QuestaSim/UVM)</li>\n <li>Experience with clock-domain-crossing tools (Questa CDC)</li>\n <li>Experience with lab bring-up and debug (Oscilloscope, Logic Analyzer, ChipScope)</li>\n <li>Active DoD Secret Clearance or higher</li>\n</ul>\n<p><strong>Workplace Options:</strong>This position is fully on-site or hybrid/flex, as mutually agreed.While on-site, you will be a part of the Scottsdale, AZ team. Learn more at https://gdmissionsystems.com/about-us/major-locations/scottsdale</p>\n<p><strong>Key Words</strong>:   Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing </p>\n<p>#LI-Hybrid</p>\n<p>#CJ1</p>\n<h2>Salary Note</h2>This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.\n<h2>Combined Salary Range</h2>USD $122,785.00 - USD $136,215.00 /Yr.\n<h2>Company Overview</h2>\n<p>General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!</p>\n<p>Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans</p>",
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