Principal DV Engineer

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work. This is a full time, exempt position, based out of our Saratoga office.  The target base pay for this position is $120,000 - $220,000 annually.  The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Why E-Space is right for you: As a member of our team, you will play a crucial role in driving our success.  Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals.  In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry. We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space: • An opportunity to really make a difference • Sustainability at our core • Fair and honest workplace • Innovative thinking is encouraged • Competitive salaries • Continuous learning and development • Health and wellness care options • Financial solutions for the future • Optional legal services (US only) • Paid holidays • Paid time off Requirements HDL & Verification Methodology · Expert-level proficiency in Verilog and SystemVerilog · Proven experience building UVM verification environments from scratch · Deep understanding of verification methodologies and best practices Programming & Scripting · Proficient in C/C++ coding for verification purposes · Strong scripting skills in Perl or Python · Ability to write and maintain bash scripts for verification flows Verification Planning & Execution · Experience writing comprehensive test plans · Experience writing and maintaining test suites · Ability to debug complex RTL simulations · Ability to debug gate-level simulations with SDF back-annotation · Ability to assess whether SDF timing violations are benign or require attention Leadership · Proven track record leading code coverage closure · Experience leading design verification efforts through chip tapeout What you bring to this role: 10+ years of design verification experience in the semiconductor industry

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