DFT Engineer

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    "datePosted": "2026-03-02",
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    "description": "<p>At <span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to <span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO) </span>of hardware systems — a critical barrier to scalable adoption.</p>\n<p><br></p>\n<p>Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology </span>powers a <span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric </span>that is both <span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution <span style=\"font-weight: bold\">reduces power consumption significantly </span>while preserving <span style=\"font-weight: bold\">high bandwidth and ultra-low latency </span>— unlocking unprecedented efficiency for AI training and inference at scale.</p>\n<p><br></p>\n<p>Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift </span>in how AI</p>\n<p>hardware is built for the future.</p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif\">We are actively seeking a resourceful <span style=\"font-weight: bold\">DFT Engineer </span><span style=\"font-weight: bold\">based in Hyderabad OR Bangalore</span></span></p>\n<p><span style=\"font-family: Inter, sans-serif\"><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif\"><span style=\"font-weight: bold\">Key Responsibilities</span>:</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif\">Hierarchical MBIST and scan insertion, BSD implementation</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">ATPG pattern generation, coverage analysis, converging to high coverage metrics</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Pattern simulations with timing</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Defining test mode timing constraints, analyzing the timing reports and converge timing</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Developing cycle accurate functional patterns using IJTAG methodology</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Closely working with the test and production engineering teams to debug and bring up devices at probe and final test</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Debugging silicon issues</span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif\"> </span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-weight: bold\">Skills:</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif\">Excellent communication skills, and strong team player with can do type of attitude</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Excellent debugging skills</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Good scripting skills to develop automation</span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif\"> </span></p>\n<p><span style=\"font-family: Inter, sans-serif\"> <span style=\"font-weight: bold\">Qualifications</span>:</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif\">5+ years of DFT experience including implementation, test pattern development, and simulation</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Proven experience in contributing to DFT solution to complex designs</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Experience working with IJTAG methodologies</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Good debug capabilities in simulating patterns with timing</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Experience with industry standard EDA tools for DFT, timing, and simulation</span></li>\n<li><span style=\"font-family: Inter, sans-serif\">Knowledge of System Verilog</span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif\"> </span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-weight: bold\">Education:</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif\">Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif\">If this is the role you have been looking for and want to be part of a growing company with an exciting future, we would really love to hear from you. Together We Kandou It!</span></p>\n<p><span style=\"font-family: Inter, sans-serif\"><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif\"><span style=\"color: rgb(34, 34, 34)\">Visit us at </span><a href=\"https://www.kandou.ai/\" target=\"_blank\" rel=\"noopener noreferrer\">www.kandou.ai</a><span style=\"color: rgb(34, 34, 34)\"> and </span><a href=\"https://www.linkedin.com/company/kandou-ai/posts?lipi=urn%3Ali%3Apage%3Acompanies_company_index%3Bd9883c75-e180-4084-9488-1a503e730cfe\" target=\"_blank\" rel=\"noopener noreferrer\">https://www.linkedin.com/company/kandou-ai/</a></span></p>",
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