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Home › Companies › 555e77b2 029a 4357 8712 1dd910b41621 19000101 000001 › Sr. Layout Engineer

Sr. Layout Engineer

555e77b2 029a 4357 8712 1dd910b41621 19000101 000001 · Rijswijk, Zuid-Holland, NL, Rijswijk, Zuid-Holland · Remote · Active · ADP Workforce Now Recruiting

Job facts

FieldValue
Company555e77b2 029a 4357 8712 1dd910b41621 19000101 000001
TitleSr. Layout Engineer
Normalized title-
Department / team-
LocationZuid-Holland, NL, Canada
Work modelRemote / Remote
Employment typeFull Time
Salary-
Statusactive
ATS providerADP Workforce Now Recruiting
Posted / first seen2026-06-05 / 2026-06-06
Changed / last seen2026-06-06 / 2026-06-06

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Linked records

Company555e77b2 029a 4357 8712 1dd910b41621 19000101 000001
Sourcec2707813-bcf1-47e7-bd8f-33621286a357
ATS providerADP Workforce Now Recruiting

Description

About SiTime SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com . Job Summary The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to develop standard layout methodologies across site. Contribute to build process and procedures to achieve high layout quality. Responsibilities: Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOScircuits Perform schematic-driven layout and design constraints Design die-area efficient layouts according to circuit designer requirements Perform block or top-level layout designs Perform floor-planning, power line planning, shielding, and device-matching layout Verify layouts. Pass DRC, LVS, and ERC Contribute to various chip-level routing and layout needs Perform chip level integration, verifications, and tape-out Support other projects as needed by management Train junior layout engineers and offshore layout contractors Contribute to develop common best practices and workflow across all sites Contribute to build process and procedures to achieve high layout quality Qualifications & Requirements: AA/AS Degree in Layout Design or related field or equivalent experience 10 years’ experience with layout design for analog and full-custom digital blocks Experience TSMC 180nm, 65nm, 22nm process technologies P roficient in using layout editing tools in the Cadence Virtuoso design environment Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints Experience in chip-level floor planning and analog block integration Experience chip level integration, verifications, and tape-out Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable Must be able to lift, push, and pull up to 5 lbs. Desired Characteristics & Attributes: Attention to detail, organized, accurate and can produce efficient layout techniques Has a good track record of on time work delivery Has a self-motivated, team player with good communication skills Ability to work well with others in a fast-paced collaborative team environment Compensation Range: At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success. SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program. Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. Innovation on Top – Philosophies of Innovation with Rajesh Vashist Fabrication Knowledge – An Interview with Rajesh Vashist SiTime Corporation – YouTube #LI-ONSITE

Full job record

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Source IDc2707813-bcf1-47e7-bd8f-33621286a357
Board IDc2707813-bcf1-47e7-bd8f-33621286a357
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Provider Job Key587261
TitleSr. Layout Engineer
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CountryCanada
RegionNL
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First Seen At2026-06-06 13:28:11Z
Last Seen At2026-06-06 13:28:11Z
Last Checked At2026-06-06 13:28:11Z
Last Changed At2026-06-06 13:28:11Z
Inactive At—
Source Posted At2026-06-05 12:43:00Z
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    "requisitionDescription": "<p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;' data-pasted=\"true\"><strong><span style=\"font-family: Arial, sans-serif; color: black; font-size: 18px;\">About SiTime</span></strong></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-family: Arial, sans-serif; color: black; font-size: 16px;\">SiTime is the Precision Timing company.&nbsp;</span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px;\"><br></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-family: Arial, sans-serif; color: black; font-size: 16px;\">Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.</span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px;\"><br></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-family: Arial, sans-serif; color: black; font-size: 16px;\">Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit:&nbsp;</span><span style=\"font-size: 16px;\"><a href=\"https://www.globenewswire.com/Tracker?data=eh05Boj9A3xOr6pxGz6VKvfwD3vaBj8ZQFOZ8KMHvM5cCnzTHKTWtWW-q-KBuKoH7G4-VSVFiVQ6RuiKbXWXfw&utm_source=sitime.com&utm_medium=site\" target=\"_blank\" title=\"(opens in a new window)\" style=\"font-size: 16px;\"><strong><span style='font-family:\"Arial\",sans-serif;'>www.sitime.com</span></strong></a></span><span style=\"font-family: Arial, sans-serif; color: black; font-size: 16px;\">.</span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px;\"><br></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 18px;\"><strong><span style=\"font-family: Arial, sans-serif;\">Job Summary</span></strong></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;margin-top:.05pt;'><span style=\"font-size: 16px;\"><br></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;margin-top:.05pt;margin-right:3.0pt;margin-bottom:.0001pt;margin-left:0in;text-align:justify;'><span style=\"font-family: Arial, sans-serif; color: black; font-size: 16px;\">The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to develop standard layout methodologies across site. Contribute to build process and procedures to achieve high layout quality.</span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;margin-top:11.3pt;margin-right:0in;margin-bottom:12.0pt;margin-left:0in;text-align:justify;'><span style=\"font-size: 18px;\"><strong><span style=\"font-family: Arial, sans-serif; color: rgb(0, 0, 0);\">Responsibilities:</span></strong></span></p><div style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;'><ul style=\"margin-bottom:0in;list-style-type: disc;margin-left: 0in;\"><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOScircuits</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Perform schematic-driven layout and design constraints</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Design die-area efficient layouts according to circuit designer requirements</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Perform block or top-level layout designs</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Perform floor-planning, power line planning, shielding, and device-matching layout</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Verify layouts. Pass DRC, LVS, and ERC</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Contribute to various chip-level routing and layout needs</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Perform chip level integration, verifications, and tape-out</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Support other projects as needed by management</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Train junior layout engineers and offshore layout contractors</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Contribute to develop common best practices and workflow across all sites</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Contribute to build process and procedures to achieve high layout&nbsp;quality</span></li></ul></div><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;margin-top:11.05pt;margin-right:0in;margin-bottom:.0001pt;margin-left:.2in;text-align:justify;'><span style=\"font-size: 18px; color: rgb(0, 0, 0);\"><strong><span style=\"font-family: Arial, sans-serif;\">Qualifications &amp; Requirements:</span></strong></span></p><div style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;'><ul style=\"margin-bottom:0in;list-style-type: disc;margin-left: 0in;\"><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">AA/AS Degree in Layout Design or related field or equivalent experience</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">10 years&rsquo; experience with layout design for analog and full-custom digital blocks</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Experience TSMC 180nm, 65nm, 22nm process technologies</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">P<span style=\"color: rgb(0, 0, 0);\">roficient in using layout editing tools in the Cadence Virtuoso design environment</span></span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Experience in chip-level floor planning and analog block integration</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Experience chip level integration, verifications, and tape-out</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Must be able to lift, push, and pull up to 5 lbs.</span></li></ul></div><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px; color: rgb(0, 0, 0);\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px; color: rgb(0, 0, 0);\"><strong><span style='font-family:\"Arial\",sans-serif;'>&nbsp; &nbsp;</span></strong></span><span style=\"font-size: 18px; color: rgb(0, 0, 0);\"><strong><span style='font-family:\"Arial\",sans-serif;'>Desired Characteristics &amp; Attributes:</span></strong></span></p><div style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;'><ul style=\"margin-bottom:0in;list-style-type: disc;margin-left: 0in;\"><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Attention to detail, organized, accurate and can produce efficient layout techniques</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Has a good track record of on time work delivery</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Has a self-motivated, team player with good communication skills</span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(0, 0, 0);\"><span style=\"font-family: Arial, sans-serif;\">Ability to work well with others in a fast-paced collaborative team environment</span></li></ul></div><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px;\"><br></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 18px;\"><strong><span style=\"font-family: Arial, sans-serif; color: rgb(0, 0, 0);\">Compensation Range: </span></strong></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px; color: rgb(0, 0, 0);\"><br></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-family: Arial, sans-serif; font-size: 16px; color: rgb(0, 0, 0);\">At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.&nbsp;</span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-family: Arial, sans-serif; font-size: 16px; color: rgb(0, 0, 0);\"><br> In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals&mdash;reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company&rsquo;s future growth and success.</span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;text-align:justify;'><span style=\"font-size: 16px;\"><br></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"font-family: Arial, sans-serif; color: black; background: white; font-size: 16px;\">SiTime is an&nbsp;</span><span style='font-family:\"Arial\",sans-serif;'><span style=\"font-size: 16px; color: rgb(44, 130, 201);\"><a href=\"http://www.sitime.com/images/EEO-is-the-law.pdf\" target=\"_blank\" style=\"font-size: 16px;\"><span style=\"background: white;\">Equal Opportunity Employer</span></a></span><span style=\"color: rgb(44, 130, 201); background: white; font-size: 16px;\">.</span><span style=\"color: black; background: white; font-size: 16px;\"> We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.</span><span style=\"color: rgb(0, 0, 0); background: white; font-size: 16px;\"> </span><span style=\"font-size: 16px; color: rgb(0, 0, 0);\">SiTime participates in the</span><span style=\"font-size: 16px; color: rgb(44, 130, 201);\"> <a href=\"http://www.sitime.com/images/E-Verify-Participation-Poster.pdf\" target=\"_blank\" style=\"color: rgb(44, 130, 201);\">E-Verify</a></span><span style=\"font-size: 16px; color: rgb(0, 0, 0);\"> program.</span></span></p><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"font-size: 18px;\"><strong><span style='font-family:\"Arial\",sans-serif;color:black;'>Learn More about SiTime:</span></strong></span><span style=\"font-size: 16px;\"><strong><span style='font-family:\"Arial\",sans-serif;color:black;'> </span></strong></span><span style=\"font-family: Arial, sans-serif; color: black; font-size: 16px;\">Review the&nbsp;</span><span style='font-family:\"Arial\",sans-serif;'><span style=\"font-size: 16px; color: rgb(44, 130, 201);\"><a href=\"https://www.sitime.com/company/careers\" target=\"_blank\" style=\"color: rgb(44, 130, 201);\">Get to Know SiTime</a></span><span style=\"color: black; font-size: 16px;\">&nbsp;section of our career page to explore our culture, values, and what makes us unique.&nbsp;</span></span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(44, 130, 201); text-align: justify;\"><span style=\"font-family: Arial, sans-serif;\"><a href=\"https://www.innovatorsontap.com/podcast/the-philosophy-of-innovation-w-rajesh-vashist\" target=\"_blank\" style=\"font-size: 16px; color: rgb(44, 130, 201);\">Innovation on Top &ndash; Philosophies of Innovation with Rajesh Vashist</a></span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(44, 130, 201); text-align: justify;\"><span style=\"font-family: Arial, sans-serif;\"><a href=\"https://www.fabricatedknowledge.com/p/an-interview-with-rajesh-vashist-3e0#details\" target=\"_blank\" style=\"font-size: 16px; color: rgb(44, 130, 201);\">Fabrication Knowledge &ndash; An Interview with Rajesh Vashist</a></span></li><li style=\"margin: 0in; font-size: 16px; font-family: Calibri, sans-serif; color: rgb(44, 130, 201); text-align: justify;\"><span style=\"font-family: Arial, sans-serif;\"><a href=\"https://www.youtube.com/user/sitimecorp/videos\" target=\"_blank\" style=\"font-size: 16px; color: rgb(44, 130, 201);\">SiTime Corporation &ndash; YouTube</a></span></li></ul><p style='margin:0in;font-size:15px;font-family:\"Calibri\",sans-serif;margin-bottom:8.0pt;line-height:115%;'><span style=\"color: white; font-size: 16px;\">#LI-ONSITE </span></p>\n",
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