Senior Staff Physical Design Engineer – Contractor/Freelance (FinFET Specialist)

{
  "content_hash": "4534759522f4e97820dfd2425062f643b1f1506b41eeb11500ecc2250946f64d",
  "source_hash": "9a7aa1d3c51b2f43ea4285933734084ed37710e319092d74dbbfb1e0235c912e",
  "last_changed_at": "2026-05-30T05:37:02.760Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "Grenoble, Grenoble, Auvergne-Rhône-Alpes, France",
    "city": "Grenoble",
    "region": "Auvergne-Rhône-Alpes",
    "country": "France",
    "is_remote": false,
    "confidence": 0.8
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-18T09:40:59.618Z",
  "launch_scope": {
    "reason": "recruitee_production_catalog",
    "included": true,
    "location": {
      "raw": "Grenoble, Grenoble, Auvergne-Rhône-Alpes, France",
      "city": "Grenoble",
      "region": "Auvergne-Rhône-Alpes",
      "country": "France",
      "is_remote": false,
      "confidence": 0.8
    },
    "countries": [
      "France"
    ]
  },
  "remote_policy": "hybrid",
  "salary_period": null,
  "workplace_type": "hybrid",
  "salary_currency": null
}

{}

{
  "id": 2521808,
  "city": "Grenoble",
  "guid": "w2p96",
  "slug": "senior-staff-physical-design-engineer-contractorfreelance-finfet-specialist",
  "tags": [],
  "title": "Senior Staff Physical Design Engineer – Contractor/Freelance (FinFET Specialist)",
  "hybrid": true,
  "remote": false,
  "salary": {
    "max": null,
    "min": null,
    "period": null,
    "currency": null
  },
  "status": "published",
  "country": "France",
  "on_site": false,
  "close_at": null,
  "location": "Grenoble, Auvergne-Rhône-Alpes, France",
  "position": 26,
  "highlight": null,
  "locations": [
    {
      "id": 245606,
      "city": "Grenoble",
      "name": "Grenoble",
      "note": null,
      "state": "Auvergne-Rhône-Alpes",
      "street": null,
      "country": "France",
      "state_code": "ARA",
      "postal_code": null,
      "country_code": "FR",
      "translations": {
        "en": {
          "city": "Grenoble",
          "name": "Grenoble",
          "note": null,
          "street": null,
          "postal_code": null
        }
      }
    }
  ],
  "max_hours": null,
  "min_hours": null,
  "created_at": "2026-03-11 10:24:04 UTC",
  "department": "Design",
  "options_cv": "required",
  "state_code": "ARA",
  "state_name": "Auvergne-Rhône-Alpes",
  "updated_at": "2026-03-23 06:44:44 UTC",
  "careers_url": "https://verticalcompute.recruitee.com/o/senior-staff-physical-design-engineer-contractorfreelance-finfet-specialist",
  "cover_image": {
    "url": "https://careers.recruiteecdn.com/image/upload/ats-production/offers/2521808/offer_cover_image_7m65wchdtvsa.png"
  },
  "description": "<p><strong><span style=\"color:#000000\">About Us</span></strong></p><p><span style=\"color:#000000\">Vertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architecture. Our mission is to redefine the well-known trade-offs of semiconductor memory devices, ultimately enabling the future of computing.</span></p><p><span style=\"color:#000000\">We are welcoming passionate, experienced, and forward-thinking colleagues to join our dynamic team and disrupt the industry together.</span></p><p style=\"min-height: 1.7em;\"></p><p><strong><span style=\"color:#000000\">About What You Will Do</span></strong></p><p><span style=\"color:#000000\">As a </span><strong><span style=\"color:#000000\">Senior Staff Physical Design Engineer</span></strong><span style=\"color:#000000\">, you will take technical leadership in the physical implementation of next-generation high-performance SoCs targeting </span><strong><span style=\"color:#000000\">16nm FinFET technologies and below</span></strong><span style=\"color:#000000\">.</span></p><p><span style=\"color:#000000\">In this role, you will:</span></p><ul><li><p><span style=\"color:#000000\">Lead the </span><strong><span style=\"color:#000000\">full RTL-to-GDSII physical implementation flow</span></strong><span style=\"color:#000000\">, including synthesis, floorplanning, place &amp; route, CTS, timing closure, and sign-off.</span></p></li><li><p><span style=\"color:#000000\">Define and execute </span><strong><span style=\"color:#000000\">implementation strategies optimized for FinFET technologies</span></strong><span style=\"color:#000000\">, addressing challenges such as secondary power grids, track patterns, and advanced DRC constraints.</span></p></li><li><p><span style=\"color:#000000\">Perform </span><strong><span style=\"color:#000000\">Multi-Mode Multi-Corner (MMMC) timing closure</span></strong><span style=\"color:#000000\"> and power optimization to achieve the best </span><strong><span style=\"color:#000000\">PPA (Power, Performance, Area)</span></strong><span style=\"color:#000000\"> targets.</span></p></li><li><p><span style=\"color:#000000\">Conduct </span><strong><span style=\"color:#000000\">power integrity analysis</span></strong><span style=\"color:#000000\"> and ensure robust IR drop and electromigration (EM) margins.</span></p></li><li><p><span style=\"color:#000000\">Drive </span><strong><span style=\"color:#000000\">physical verification closure</span></strong><span style=\"color:#000000\"> including DRC, LVS, ERC, and antenna checks using industry-standard sign-off tools.</span></p></li><li><p><span style=\"color:#000000\">Collaborate closely with </span><strong><span style=\"color:#000000\">RTL and DFT teams</span></strong><span style=\"color:#000000\"> to ensure physically aware synthesis, efficient scan-chain integration, and congestion mitigation.</span></p></li><li><p><span style=\"color:#000000\">Interface with </span><strong><span style=\"color:#000000\">foundries and EDA vendors</span></strong><span style=\"color:#000000\"> to address technology-specific implementation challenges.</span></p></li><li><p><span style=\"color:#000000\">Contribute to </span><strong><span style=\"color:#000000\">EDA flow improvements and automation</span></strong><span style=\"color:#000000\"> through scripting (Tcl, Python, or Perl) to enhance productivity and design quality.</span></p></li><li><p><span style=\"color:#000000\">Act as a </span><strong><span style=\"color:#000000\">technical pillar and mentor</span></strong><span style=\"color:#000000\"> within the physical design team, supporting complex debugging and advanced optimization strategies.</span></p></li></ul><p style=\"min-height: 1.7em;\"></p>",
  "postal_code": null,
  "company_name": "Vertical Compute",
  "country_code": "FR",
  "published_at": "2026-03-16 09:55:53 UTC",
  "requirements": "<p><strong><span style=\"color:#000000\">About who you are:</span></strong></p><ul><li><p><span style=\"color:#000000\">Master’s in Electrical Engineering or related field.</span></p></li><li><p><span style=\"color:#000000\">10+ years in full-custom layout for memory and/or analog/mixed-signal IPs.</span></p></li><li><p><span style=\"color:#000000\">Deep understanding of physical constraints: matching, EM, IR drop, antenna rules.</span></p></li><li><p><span style=\"color:#000000\">Proficient in layout tools (Virtuoso, Calibre), proficiency in CAD scripting is considered as a big plus.</span></p></li><li><p><span style=\"color:#000000\">Experience with advanced CMOS nodes and emerging memories (MRAM, RRAM) is a plus.</span></p></li><li><p><span style=\"color:#000000\">Experience in in-memory computing layout is a plus.</span></p></li><li><p><span style=\"color:#000000\">Self-motivated, self-directed, and well-organized.</span></p></li><li><p><span style=\"color:#000000\">We like to build a high performing dream team and count on your excellent communication and interpersonal skills, and ability to engage effectively with your colleagues, our partners, and stakeholders.</span></p></li><li><p><span style=\"color:#000000\">Good English communication skills, knowledge of French and/or Dutch is considered a bonus.</span></p></li></ul><p style=\"min-height: 1.7em;\"></p><p><strong><span style=\"color:#000000\">Why Join Us:</span></strong></p><ul><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">You will get the opportunity to work at the forefront of memory technology innovation.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">You can be part of a talented and dedicated team in a fast-paced startup environment.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">You can count on a motivating total rewards package.</span></p></li></ul><p><br></p><p><strong><span style=\"color:#000000\">How to show your interest in our vacancy:</span></strong><span style=\"color:#000000\"> Does the above sounds like you are ready to join our team, please upload your CV.</span></p><p style=\"min-height: 1.7em;\"></p><p><span style=\"color:#000000\">Vertical Compute is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.</span></p><p><span style=\"color:#000000\">Join us in shaping the future of compute &amp; memory technology and celebrating success!</span></p><p><br><br><br></p><p style=\"min-height: 1.7em;\"></p>",
  "translations": {
    "en": {
      "title": "Senior Staff Physical Design Engineer – Contractor/Freelance (FinFET Specialist)",
      "highlight": null,
      "description": "<p><strong><span style=\"color:#000000\">About Us</span></strong></p><p><span style=\"color:#000000\">Vertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architecture. Our mission is to redefine the well-known trade-offs of semiconductor memory devices, ultimately enabling the future of computing.</span></p><p><span style=\"color:#000000\">We are welcoming passionate, experienced, and forward-thinking colleagues to join our dynamic team and disrupt the industry together.</span></p><p style=\"min-height: 1.7em;\"></p><p><strong><span style=\"color:#000000\">About What You Will Do</span></strong></p><p><span style=\"color:#000000\">As a </span><strong><span style=\"color:#000000\">Senior Staff Physical Design Engineer</span></strong><span style=\"color:#000000\">, you will take technical leadership in the physical implementation of next-generation high-performance SoCs targeting </span><strong><span style=\"color:#000000\">16nm FinFET technologies and below</span></strong><span style=\"color:#000000\">.</span></p><p><span style=\"color:#000000\">In this role, you will:</span></p><ul><li><p><span style=\"color:#000000\">Lead the </span><strong><span style=\"color:#000000\">full RTL-to-GDSII physical implementation flow</span></strong><span style=\"color:#000000\">, including synthesis, floorplanning, place &amp; route, CTS, timing closure, and sign-off.</span></p></li><li><p><span style=\"color:#000000\">Define and execute </span><strong><span style=\"color:#000000\">implementation strategies optimized for FinFET technologies</span></strong><span style=\"color:#000000\">, addressing challenges such as secondary power grids, track patterns, and advanced DRC constraints.</span></p></li><li><p><span style=\"color:#000000\">Perform </span><strong><span style=\"color:#000000\">Multi-Mode Multi-Corner (MMMC) timing closure</span></strong><span style=\"color:#000000\"> and power optimization to achieve the best </span><strong><span style=\"color:#000000\">PPA (Power, Performance, Area)</span></strong><span style=\"color:#000000\"> targets.</span></p></li><li><p><span style=\"color:#000000\">Conduct </span><strong><span style=\"color:#000000\">power integrity analysis</span></strong><span style=\"color:#000000\"> and ensure robust IR drop and electromigration (EM) margins.</span></p></li><li><p><span style=\"color:#000000\">Drive </span><strong><span style=\"color:#000000\">physical verification closure</span></strong><span style=\"color:#000000\"> including DRC, LVS, ERC, and antenna checks using industry-standard sign-off tools.</span></p></li><li><p><span style=\"color:#000000\">Collaborate closely with </span><strong><span style=\"color:#000000\">RTL and DFT teams</span></strong><span style=\"color:#000000\"> to ensure physically aware synthesis, efficient scan-chain integration, and congestion mitigation.</span></p></li><li><p><span style=\"color:#000000\">Interface with </span><strong><span style=\"color:#000000\">foundries and EDA vendors</span></strong><span style=\"color:#000000\"> to address technology-specific implementation challenges.</span></p></li><li><p><span style=\"color:#000000\">Contribute to </span><strong><span style=\"color:#000000\">EDA flow improvements and automation</span></strong><span style=\"color:#000000\"> through scripting (Tcl, Python, or Perl) to enhance productivity and design quality.</span></p></li><li><p><span style=\"color:#000000\">Act as a </span><strong><span style=\"color:#000000\">technical pillar and mentor</span></strong><span style=\"color:#000000\"> within the physical design team, supporting complex debugging and advanced optimization strategies.</span></p></li></ul><p style=\"min-height: 1.7em;\"></p>",
      "requirements": "<p><strong><span style=\"color:#000000\">About who you are:</span></strong></p><ul><li><p><span style=\"color:#000000\">Master’s in Electrical Engineering or related field.</span></p></li><li><p><span style=\"color:#000000\">10+ years in full-custom layout for memory and/or analog/mixed-signal IPs.</span></p></li><li><p><span style=\"color:#000000\">Deep understanding of physical constraints: matching, EM, IR drop, antenna rules.</span></p></li><li><p><span style=\"color:#000000\">Proficient in layout tools (Virtuoso, Calibre), proficiency in CAD scripting is considered as a big plus.</span></p></li><li><p><span style=\"color:#000000\">Experience with advanced CMOS nodes and emerging memories (MRAM, RRAM) is a plus.</span></p></li><li><p><span style=\"color:#000000\">Experience in in-memory computing layout is a plus.</span></p></li><li><p><span style=\"color:#000000\">Self-motivated, self-directed, and well-organized.</span></p></li><li><p><span style=\"color:#000000\">We like to build a high performing dream team and count on your excellent communication and interpersonal skills, and ability to engage effectively with your colleagues, our partners, and stakeholders.</span></p></li><li><p><span style=\"color:#000000\">Good English communication skills, knowledge of French and/or Dutch is considered a bonus.</span></p></li></ul><p style=\"min-height: 1.7em;\"></p><p><strong><span style=\"color:#000000\">Why Join Us:</span></strong></p><ul><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">You will get the opportunity to work at the forefront of memory technology innovation.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">You can be part of a talented and dedicated team in a fast-paced startup environment.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.</span></p></li><li><p style=\"text-align:justify;\"><span style=\"color:#000000\">You can count on a motivating total rewards package.</span></p></li></ul><p><br></p><p><strong><span style=\"color:#000000\">How to show your interest in our vacancy:</span></strong><span style=\"color:#000000\"> Does the above sounds like you are ready to join our team, please upload your CV.</span></p><p style=\"min-height: 1.7em;\"></p><p><span style=\"color:#000000\">Vertical Compute is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.</span></p><p><span style=\"color:#000000\">Join us in shaping the future of compute &amp; memory technology and celebrating success!</span></p><p><br><br><br></p><p style=\"min-height: 1.7em;\"></p>",
      "sharing_image": "https://recruitee-main.s3.eu-central-1.amazonaws.com/offers/2521808/normal_sharing_729ee9p16kck.png",
      "sharing_title": "Senior Staff Physical Design Engineer – Contractor/Freelance (FinFET Specialist)",
      "locations_question": "What is your preferred work location?",
      "sharing_description": "About UsVertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architecture. Our mission is to redefine the well-known "
    }
  },
  "category_code": "engineering",
  "mailbox_email": "[email protected]",
  "options_phone": "required",
  "options_photo": "off",
  "options_title": "off",
  "sharing_image": "https://recruitee-main.s3.eu-central-1.amazonaws.com/offers/2521808/normal_sharing_729ee9p16kck.png",
  "sharing_title": "Senior Staff Physical Design Engineer – Contractor/Freelance (FinFET Specialist)",
  "dynamic_fields": [],
  "education_code": "master_degree",
  "open_questions": [],
  "experience_code": "experienced",
  "careers_apply_url": "https://verticalcompute.recruitee.com/o/senior-staff-physical-design-engineer-contractorfreelance-finfet-specialist/c/new",
  "locations_question": "What is your preferred work location?",
  "max_hours_per_week": null,
  "min_hours_per_week": null,
  "options_salutation": "off",
  "sharing_description": "About UsVertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architecture. Our mission is to redefine the well-known ",
  "employment_type_code": "fulltime_permanent",
  "options_cover_letter": "optional",
  "locations_question_type": "multiple_choice",
  "location_question_visible": false,
  "locations_question_required": true
}