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HomeCompaniesCareers Latticesemi Icims ComDir, CAD Eng • R&D

Dir, CAD Eng • R&D

Careers Latticesemi Icims Com · San Jose, CA, US · Active · iCIMS

Job facts

FieldValue
CompanyCareers Latticesemi Icims Com
TitleDir, CAD Eng • R&D
Normalized title-
Department / teamEngineering
LocationSan Jose, CA, United States
Work model-
Employment typeFull Time
Salary-
Statusactive
ATS provideriCIMS
Posted / first seen2026-06-10 / 2026-06-10
Changed / last seen2026-06-17 / 2026-06-18

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City jobsActive postings in San Jose.Open
Department jobsActive postings in Engineering.Open
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Linked records

CompanyCareers Latticesemi Icims Com
Source333bd52c-d270-4ffb-884d-96d5ce6e1787
ATS provideriCIMS

Description

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Description: Director – CAD Design Engineering & EDA Infrastructure Role Overview The Director of EDA Design Methodology & Infrastructure will lead the development, deployment, and optimization of design automation flows, tools, and infrastructure across the organization. This role ensures that engineering teams have cutting-edge, scalable, and efficient methodologies to deliver complex semiconductor designs on time and with high quality. Key Responsibilities EDA Strategy : Define and drive the long-term vision for EDA methodologies, flows, and infrastructure to support advanced semiconductor design. Methodology Development : Architect and implement design flows for RTL-to-GDSII, verification, physical design, timing closure, and sign-off. Infrastructure Management : Oversee compute farms, license servers, cloud integration, and tool deployment to ensure scalability and efficiency. GenAI Strategy for the EDA Design and Methodology Cross-functional Collaboration : Partner with design, verification, CAD, and IT teams to align methodologies with project needs. Tool Evaluation : Evaluate, benchmark, and deploy EDA tools from major vendors; negotiate with suppliers to optimize cost and performance. Innovation Leadership : Introduce automation, AI/ML-driven flows, and cloud-native solutions to accelerate design productivity. Team Leadership : Build and mentor a high-performing team of CAD/EDA engineers; foster a culture of technical excellence and innovation. Process Standardization : Establish best practices, documentation, and training programs for design teams worldwide. Risk Management : Identify and mitigate risks in tool flows, infrastructure, and project schedules. Qualifications Education : Master’s in electrical engineering, Computer Engineering, or related field. Experience : 15+ years in semiconductor design, with at least 7 years in EDA methodology leadership. Technical Expertise : Deep knowledge of RTL design, verification, synthesis, place & route, timing analysis, and sign-off flows. Infrastructure Knowledge : Strong background in compute infrastructure, cloud-based design environments, and license management. Leadership Skills : Proven ability to lead global teams, manage vendor relationships, and drive organizational change. Soft Skills : Excellent communication, negotiation, and strategic planning abilities. Impact This role is pivotal in enabling the company to design next-generation chips efficiently and competitively. By leading EDA methodology and infrastructure, the director ensures that engineering teams can innovate faster, reduce time-to-market, and maintain design quality at scale.

Full job record

Job IDae51935f51254f0bfa2563a17e635f9a46f0ca96
Org ID959cab7a-f3a8-43a5-a974-5a62f522424b
Source ID333bd52c-d270-4ffb-884d-96d5ce6e1787
Board ID333bd52c-d270-4ffb-884d-96d5ce6e1787
Providericims
Provider Job Key3682
TitleDir, CAD Eng • R&D
Normalized Title
Statusactive
Activeyes
Location TextSan Jose, CA, US
DepartmentEngineering
Team
Employment Typefull_time
Workplace Type
Remote Policy
CountryUnited States
RegionCA
CitySan Jose
Salary RawLattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Description: Director – CAD Design Engineering & EDA Infrastructure Role Overview The Director of EDA Design Methodology & Infrastructure will lead the development, deployment, and optimization of design automation flows, tools, and infrastructure across the organization. This role ensures that engineering teams have cutting-edge, scalable, and efficient methodologies to deliver complex semiconductor designs on time and with high quality. Key Responsibilities EDA Strategy : Define and drive the long-term vision for EDA methodologies, flows, and infrastructure to support advanced semiconductor design. Methodology Development : Architect and implement design flows for RTL-to-GDSII, verification, physical design, timing closure, and sign-off. Infrastructure Management : Oversee compute farms, license servers, cloud integration, and tool deployment to ensure scalability and efficiency. GenAI Strategy for the EDA Design and Methodology Cross-functional Collaboration : Partner with design, verification, CAD, and IT teams to align methodologies with project needs. Tool Evaluation : Evaluate, benchmark, and deploy EDA tools from major vendors; negotiate with suppliers to optimize cost and performance. Innovation Leadership : Introduce automation, AI/ML-driven flows, and cloud-native solutions to accelerate design productivity. Team Leadership : Build and mentor a high-performing team of CAD/EDA engineers; foster a culture of technical excellence and innovation. Process Standardization : Establish best practices, documentation, and training programs for design teams worldwide. Risk Management : Identify and mitigate risks in tool flows, infrastructure, and project schedules. Qualifications Education : Master’s in electrical engineering, Computer Engineering, or related field. Experience : 15+ years in semiconductor design, with at least 7 years in EDA methodology leadership. Technical Expertise : Deep knowledge of RTL design, verification, synthesis, place & route, timing analysis, and sign-off flows. Infrastructure Knowledge : Strong background in compute infrastructure, cloud-based design environments, and license management. Leadership Skills : Proven ability to lead global teams, manage vendor relationships, and drive organizational change. Soft Skills : Excellent communication, negotiation, and strategic planning abilities. Impact This role is pivotal in enabling the company to design next-generation chips efficiently and competitively. By leading EDA methodology and infrastructure, the director ensures that engineering teams can innovate faster, reduce time-to-market, and maintain design quality at scale.
Salary Min
Salary Max
Salary Currency
Salary Period
Source URLhttps://careers-latticesemi.icims.com/jobs/3682/dir%2c-cad-eng-%e2%80%a2-r%26d/job
Apply URLhttps://careers-latticesemi.icims.com/jobs/3682/dir%2c-cad-eng-%e2%80%a2-r%26d/job
First Seen At2026-06-10 08:19:09Z
Last Seen At2026-06-18 08:21:41Z
Last Checked At2026-06-18 08:21:41Z
Last Changed At2026-06-17 08:14:42Z
Inactive At
Source Posted At2026-06-10 04:00:00Z
Source Updated At
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=icims/board=careers-latticesemi.icims.com/date=2026-06-18/2026-06-18T08-21-39-347Z-856c56e0d3c3c7164fef02fe7dd0e7c4d3c87ded3b7216fd08ca4acbdb1a6cd5.json
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