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ASIC Diagnostic & Silicon Bring-Up Engineer

Eridu · Saratoga, CA, United States · On Site · Active · $180,000–$250,000 / year · Rippling ATS

Job facts

FieldValue
CompanyEridu
TitleASIC Diagnostic & Silicon Bring-Up Engineer
Normalized title-
Department / teamASIC Engineering
LocationSaratoga, CA, United States
Work modelOn Site
Employment typeFull Time
Salary$180,000–$250,000 / year
Statusactive
ATS providerRippling ATS
Posted / first seen2026-04-30 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

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Company jobsActive postings from Eridu.Open
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ATS provider jobsActive postings observed through Rippling ATS.Open
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City jobsActive postings in Saratoga.Open
Department jobsActive postings in ASIC Engineering.Open
Work model jobsActive On Site postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyEridu
Source2e3b3faf-1f18-443b-b03c-ab436c316a6b
ATS providerRippling ATS

Description

company About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability. The company’s solutions and value proposition have been widely validated by leading hyperscalers. Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems. Visit our website eridu.ai to learn more. role Position Overview We are looking for a Senior ASIC Diagnostics Engineer to drive post-silicon bring-up, debug, and validation of next-generation high-performance ASICs. This role focuses on building diagnostic infrastructure, automation frameworks, and debug tools to validate ASIC functionality across SERDES, high-speed interfaces, and packet processing pipelines. The ideal candidate is hands-on, software-driven, and comfortable debugging across RTL, firmware, and silicon. Key Responsibilities Develop diagnostics for early silicon validation and debug Lead bring-up of ASIC silicon on characterization and validation platforms Validate power, reset, and clocking sequences, along with register access and initialization flows Design and build Python-based diagnostic frameworks for register access, configuration management, and test orchestration; convert debug procedures into automated test flows Develop diagnostics for SERDES links (training, BER, eye margining), Ethernet, PCIe, and UCIe / chiplet interfaces Use SDKs and internal tools to generate traffic, verify data path correctness, and validate counters and statistics Integrate and correlate behavior across RTL verification, emulation platforms, and silicon; develop correlation tools and methodologies Perform deep debug across ASIC logic, interfaces, and firmware interactions; isolate functional mismatches, timing/clocking issues, and protocol failures Develop automated diagnostics and integrate into regression frameworks and continuous validation pipelines Required Qualifications Bachelor’s with 10+ years or Master’s with 5+ years of relevant experience Strong experience in ASIC bring-up / post-silicon validation and hardware-software debug Strong programming skills in Python (mandatory), along with C/C++ and scripting Experience building diagnostic frameworks, automation tools, and test orchestration systems Preferred Qualifications Experience with SERDES , UCIe / chiplet architectures, or networking ASICs Familiarity with packet processor SDKs and emulation platforms Experience with BER testing tools and SERDES tuning/margining Exposure to CI/regression infrastructure for silicon validation Why Join Us? At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. Notice to Recruiting Agencies Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

Full job record

Job IDad19b49c92a1801e43d91441391b73f80578db06
Org IDd05d9cdc-fa71-444b-b57a-6140fe525606
Source ID2e3b3faf-1f18-443b-b03c-ab436c316a6b
Board ID2e3b3faf-1f18-443b-b03c-ab436c316a6b
Providerrippling
Provider Job Key446220b0-0e9a-424a-b5b3-41b2404f04e2
TitleASIC Diagnostic & Silicon Bring-Up Engineer
Normalized Title—
Statusactive
Activeyes
Location TextSaratoga, CA, United States
DepartmentASIC Engineering
Team—
Employment Typefull_time
Workplace Typeon_site
Remote Policy—
CountryUnited States
RegionCA
CitySaratoga
Salary RawUSD 180000-250000 YEAR
Salary Min180,000
Salary Max250,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://ats.rippling.com/eridu-ai/jobs/446220b0-0e9a-424a-b5b3-41b2404f04e2
Apply URLhttps://ats.rippling.com/eridu-ai/jobs/446220b0-0e9a-424a-b5b3-41b2404f04e2
First Seen At2026-05-29 07:14:02Z
Last Seen At2026-06-06 19:44:35Z
Last Checked At2026-06-06 19:44:35Z
Last Changed At2026-06-06 19:44:35Z
Inactive At—
Source Posted At2026-04-30 19:03:48Z
Source Updated At—
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      "role": "<meta><h5 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0px;margin-top:10px;margin-bottom:4px;text-align:start;padding-left:0px;\"><span style=\"background-color:rgb(255,255,255);white-space:pre-wrap;\">Position Overview</span></h5><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><span style=\"background-color:rgba(0,0,0,0);white-space:pre-wrap;\">We are looking for a Senior ASIC Diagnostics Engineer&nbsp;to drive post-silicon bring-up, debug, and validation of next-generation high-performance ASICs. This role focuses on building diagnostic infrastructure, automation frameworks, and debug tools to validate ASIC functionality across SERDES, high-speed interfaces, and packet processing pipelines.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><span style=\"background-color:rgba(0,0,0,0);white-space:pre-wrap;\">The ideal candidate is hands-on, software-driven, and comfortable debugging across RTL, firmware, and silicon.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><h5 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0px;margin-top:10px;margin-bottom:4px;text-align:start;padding-left:0px;\"><span style=\"background-color:rgb(255,255,255);white-space:pre-wrap;\">Key Responsibilities</span></h5><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Develop diagnostics for early silicon validation and debug</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Lead bring-up of ASIC silicon on characterization and validation platforms</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Validate power, reset, and clocking sequences, along with register access and initialization flows</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Design and build Python-based diagnostic frameworks for register access, configuration management, and test orchestration; convert debug procedures into automated test flows</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Develop diagnostics for SERDES links (training, BER, eye margining), Ethernet, PCIe, and UCIe / chiplet interfaces</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Use SDKs and internal tools to generate traffic, verify data path correctness, and validate counters and statistics</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Integrate and correlate behavior across RTL verification, emulation platforms, and silicon; develop correlation tools and methodologies</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Perform deep debug across ASIC logic, interfaces, and firmware interactions; isolate functional mismatches, timing/clocking issues, and protocol failures</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Develop automated diagnostics and integrate into regression frameworks and continuous validation pipelines</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><h5 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0px;margin-top:10px;margin-bottom:4px;text-align:start;padding-left:0px;\"><span style=\"background-color:rgb(255,255,255);white-space:pre-wrap;\">Required Qualifications</span></h5><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Bachelor’s with 10+ years or Master’s with 5+ years of relevant experience</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Strong experience in ASIC bring-up / post-silicon validation and hardware-software debug</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Strong programming skills in Python (mandatory), along with C/C++ and scripting</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Experience building diagnostic frameworks, automation tools, and test orchestration systems</span><br><br></li></ul><h5 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0px;margin-top:10px;margin-bottom:4px;text-align:start;padding-left:0px;\"><span style=\"background-color:rgb(255,255,255);white-space:pre-wrap;\">Preferred Qualifications</span></h5><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Experience with SERDES , UCIe / chiplet architectures, or networking ASICs</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Familiarity with packet processor SDKs and emulation platforms</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Experience with BER testing&nbsp;tools and SERDES tuning/margining</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:start;\"><span style=\"white-space:pre-wrap;\">Exposure to CI/regression infrastructure for silicon&nbsp;validation</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><br></p><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;text-align:start;padding-left:0px;\"><b><strong style=\"color:black;white-space:pre-wrap;\">Why Join Us?&nbsp;</strong></b></h4><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><br></p><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Notice to Recruiting Agencies</strong></b></h6><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.</span></p>",
      "company": "<meta><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">About Eridu</strong></b></h4><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver </span><i><em style=\"font-size:11pt;white-space:pre-wrap;\">Faster AI</em></i><span style=\"font-size:11pt;white-space:pre-wrap;\">. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">The company’s solutions and value proposition have been widely validated by leading hyperscalers.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Visit our website </span><a href=\"http://eridu.ai\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(30,74,169);cursor:pointer;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">eridu.ai</span></a><span style=\"font-size:11pt;white-space:pre-wrap;\"> to learn more.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:left;\"><br></p>"
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GET https://api.bluedoor.sh/job-postings/v1/jobs/ad19b49c92a1801e43d91441391b73f80578db06?include=descriptionJSON
GET https://api.bluedoor.sh/job-postings/v1/orgs/d05d9cdc-fa71-444b-b57a-6140fe525606JSON
GET https://api.bluedoor.sh/job-postings/v1/sources/2e3b3faf-1f18-443b-b03c-ab436c316a6bJSON
GET https://api.bluedoor.sh/job-postings/v1/jobs/ad19b49c92a1801e43d91441391b73f80578db06/eventsJSON

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