Home › Companies › Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1 › Manufacturing Engineer – PIC wafer fabrication
Manufacturing Engineer – PIC wafer fabrication
Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1 · United States; Infinera Caspian Dr, Sunnyvale, California, US · Active · Oracle Recruiting Cloud / Fusion HCM
Job facts
| Field | Value |
|---|---|
| Company | Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1 |
| Title | Manufacturing Engineer – PIC wafer fabrication |
| Normalized title | - |
| Department / team | Applied R&D |
| Location | United States |
| Work model | - |
| Employment type | Full Time |
| Salary | - |
| Status | active |
| ATS provider | Oracle Recruiting Cloud / Fusion HCM |
| Posted / first seen | 2026-05-05 / 2026-05-31 |
| Changed / last seen | 2026-05-31 / 2026-06-06 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through Oracle Recruiting Cloud / Fusion HCM. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| Department jobs | Active postings in Applied R&D. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1 |
| Source | dbfc4c22-73ba-4fc5-9705-234e3e914c7c |
| ATS provider | Oracle Recruiting Cloud / Fusion HCM |
Description
Description
In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise
Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.
Responsibilities
Optimize plasma deposition, plasma etch, wet etch and clean, and related processes needed for PIC wafer fabrication. Work in teams to scale PIC wafer fabrication processes to larger wafer sizes, while meeting key objectives for PIC yield, uniformity, and end-of-line parametric performance. Troubleshoot wafer fabrication process problems to enable a smooth flow of production and development wafers in the fab. Support engineering process and tool owners in resolving fab process or equipment problems. Execute fabrication work and data collection to support process development for etch, and deposition, and photolithography roadmap activities needed for future PIC technology. Utilize metrology equipment and test structures to maintain process control across wafer fab process modules, improve production yield and enable and guide new process development.
Qualifications
JMP, DOE, SPC and their application to semiconductor manufacturing Working knowledge of semiconductor fabrication processes, and expertise in etch, deposition, photolithography and related processes. Strong initiative, leadership and communication skills. Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume. Experience supporting a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution.
Education/Experience Required: B.S degree or equivalent experience.
Preferred Knowledge/Skills/Abilities:
Technical depth in aspects of, etch, deposition, photolithography or similar tools and processes used for semiconductor manufacturing. 5 years’ experience in broad aspects of semiconductor wafer fabrication. Knowledge of wafer fab metrology tools, for example ellipsometry, CD-SEM, step height, and overlay metrology Clear communication of problems, challenges, and initiative in deploying solutions. A working knowledge and fab experience from pathfinding through mature production. A compound semiconductor background is a plus Same Posting Description for Internal and External Candidates
Company
Come create the technology that helps the world act together
Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world.
We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work
What we offer
Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered.
Nokia is committed to inclusion and is an equal opportunity employer
Nokia has received the following recognitions for its commitment to inclusion & equality:
One of the World’s Most Ethical Companies by Ethisphere
Gender-Equality Index by Bloomberg
Workplace Pride Global Benchmark
At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.
Join us and be part of a company where you will feel included and empowered to succeed.
Additional Information
US/Canada Nokia Offers a comprehensive benefits package that includes but is not limited to:
Corporate Retirement Savings Plan
Health and dental benefits
Short-term disability, and long-term disability
Life insurance, and AD&D – Company paid 2x base pay
Optional or Supplemental life and AD&D insurance (Employee/Spouse/Child)
Paid time off for holidays and Vacation
Employee Stock Purchase Plan
Tuition Assistance Plan
Adoption assistance
Employee Assistance Program/Work Life Resource Program
The above benefits exclude students.
Disclaimer for US/Canada
Nokia Maintains broad annual base salary ranges for its roles in order to account for variations in knowledge, skills, experience and market conditions, and with consideration to internal peer equity.( Check the salary ranges in the job info section for this role )
All North America job posts will post for a minimum of 7 calendar days and up to 180 days or until candidate/s identified.
Full job record
| Job ID | a5c668254552cc817e006cbb10ec46231f2ea071 |
| Org ID | 0229f528-a584-4e4f-9943-249cfaac294e |
| Source ID | dbfc4c22-73ba-4fc5-9705-234e3e914c7c |
| Board ID | dbfc4c22-73ba-4fc5-9705-234e3e914c7c |
| Provider | oracle_hcm |
| Provider Job Key | 23288 |
| Title | Manufacturing Engineer – PIC wafer fabrication |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | United States; Infinera Caspian Dr, Sunnyvale, California, US |
| Department | Applied R&D |
| Team | — |
| Employment Type | full_time |
| Workplace Type | — |
| Remote Policy | — |
| Country | United States |
| Region | — |
| City | — |
| Salary Raw | Description In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. Responsibilities Optimize plasma deposition, plasma etch, wet etch and clean, and related processes needed for PIC wafer fabrication. Work in teams to scale PIC wafer fabrication processes to larger wafer sizes, while meeting key objectives for PIC yield, uniformity, and end-of-line parametric performance. Troubleshoot wafer fabrication process problems to enable a smooth flow of production and development wafers in the fab. Support engineering process and tool owners in resolving fab process or equipment problems. Execute fabrication work and data collection to support process development for etch, and deposition, and photolithography roadmap activities needed for future PIC technology. Utilize metrology equipment and test structures to maintain process control across wafer fab process modules, improve production yield and enable and guide new process development. Qualifications JMP, DOE, SPC and their application to semiconductor manufacturing Working knowledge of semiconductor fabrication processes, and expertise in etch, deposition, photolithography and related processes. Strong initiative, leadership and communication skills. Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume. Experience supporting a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution. Education/Experience Required: B.S degree or equivalent experience. Preferred Knowledge/Skills/Abilities: Technical depth in aspects of, etch, deposition, photolithography or similar tools and processes used for semiconductor manufacturing. 5 years’ experience in broad aspects of semiconductor wafer fabrication. Knowledge of wafer fab metrology tools, for example ellipsometry, CD-SEM, step height, and overlay metrology Clear communication of problems, challenges, and initiative in deploying solutions. A working knowledge and fab experience from pathfinding through mature production. A compound semiconductor background is a plus Same Posting Description for Internal and External Candidates Company Come create the technology that helps the world act together Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world. We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work What we offer Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered. Nokia is committed to inclusion and is an equal opportunity employer Nokia has received the following recognitions for its commitment to inclusion & equality: One of the World’s Most Ethical Companies by Ethisphere Gender-Equality Index by Bloomberg Workplace Pride Global Benchmark At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect. Join us and be part of a company where you will feel included and empowered to succeed. Additional Information US/Canada Nokia Offers a comprehensive benefits package that includes but is not limited to: Corporate Retirement Savings Plan Health and dental benefits Short-term disability, and long-term disability Life insurance, and AD&D – Company paid 2x base pay Optional or Supplemental life and AD&D insurance (Employee/Spouse/Child) Paid time off for holidays and Vacation Employee Stock Purchase Plan Tuition Assistance Plan Adoption assistance Employee Assistance Program/Work Life Resource Program The above benefits exclude students. Disclaimer for US/Canada Nokia Maintains broad annual base salary ranges for its roles in order to account for variations in knowledge, skills, experience and market conditions, and with consideration to internal peer equity.( Check the salary ranges in the job info section for this role ) All North America job posts will post for a minimum of 7 calendar days and up to 180 days or until candidate/s identified. |
| Salary Min | — |
| Salary Max | — |
| Salary Currency | — |
| Salary Period | — |
| Source URL | https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/23288 |
| Apply URL | https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/23288 |
| First Seen At | 2026-05-31 18:14:26Z |
| Last Seen At | 2026-06-06 11:52:08Z |
| Last Checked At | 2026-06-06 11:52:08Z |
| Last Changed At | 2026-05-31 18:14:26Z |
| Inactive At | — |
| Source Posted At | 2026-05-05 00:32:10Z |
| Source Updated At | — |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=oracle_hcm/board=fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com|CX_1/date=2026-06-06/2026-06-06T11-50-57-105Z-db7c626ded2e30266b558cc1a4d87fc8b3f6104e934978156486dc201f37d376.json |
Event Fields
{
"content_hash": "04a7f34f51f9fc0220b82005a00934c8e68335f7cca5a1229b7a860582de9580",
"source_hash": "46f112c6f9950a90f1b10e278efbb314aa0ed8de52943449fd7cdf51cb85263e",
"last_changed_at": "2026-05-31T18:14:26.156Z",
"active_status": "active"
}Parsed Structured
{
"language": "en",
"location": {
"raw": "United States",
"city": null,
"region": null,
"country": "United States",
"is_remote": false,
"confidence": 0.8
},
"salary_max": null,
"salary_min": null,
"inferred_at": "2026-06-06T11:52:07.635Z",
"launch_scope": {
"reason": "english_us_canada",
"included": true,
"language": "en",
"location": {
"raw": "United States",
"city": null,
"region": null,
"country": "United States",
"is_remote": false,
"confidence": 0.8
},
"countries": [
"United States"
]
},
"remote_policy": null,
"salary_period": null,
"workplace_type": null,
"salary_currency": null
}Extensions
{}Native Structured
{
"detail": {
"Id": "23288",
"Title": "Manufacturing Engineer – PIC wafer fabrication",
"media": [],
"skills": [],
"JobType": "Experienced",
"Category": "Applied R&D",
"JobGrade": null,
"JobLevel": null,
"JobShift": null,
"WorkDays": null,
"WorkHours": null,
"WorkYears": null,
"Department": null,
"HotJobFlag": false,
"StudyLevel": "High school diploma (B-levels)",
"WorkMonths": null,
"WorkerType": null,
"GeographyId": 300000000480126,
"JobFamilyId": 300000009357764,
"JobFunction": "Digital Hardware",
"JobSchedule": "Full time",
"BusinessUnit": null,
"ContractType": null,
"Organization": null,
"TrendingFlag": true,
"workLocation": [
{
"Country": "US",
"Region1": null,
"Region2": "California",
"Region3": null,
"Building": null,
"Latitude": "37.4023",
"Longitude": "-122.00764",
"LocationId": 300000892203459,
"PostalCode": "94089-1015",
"TownOrCity": "Sunnyvale",
"AddressLine1": "255 Caspian Drive",
"AddressLine2": null,
"AddressLine3": null,
"AddressLine4": null,
"LocationName": "Infinera Caspian Dr"
}
],
"ContentLocale": "en",
"HiringManager": null,
"LegalEmployer": null,
"RequisitionId": 300001233887293,
"WorkplaceType": "",
"BusinessUnitId": 300000006664259,
"OrganizationId": 300000806573851,
"GeographyNodeId": 100000448855450,
"JobFunctionCode": "DHA",
"LegalEmployerId": 300001149319675,
"PrimaryLocation": "United States",
"RequisitionType": "Standard (Internal & External)",
"NumberOfOpenings": null,
"WorkplaceTypeCode": null,
"BeFirstToApplyFlag": false,
"otherWorkLocations": [],
"secondaryLocations": [],
"ExternalContactName": null,
"ShortDescriptionStr": "Support a balance of sustaining, optimization, and qualification of wafer fabrication processes, including etch, and deposition and photolithography. These processes are applied to both existing and new technology generations of Photonic Integrated Circuits (PICs). Participate in the development of wafer process recipes, operational procedures, and provide other support needed to qualify new tools needed for the release of an additional PIC wafer manufacturing site. Collect, interpret, and respond to wafer fab statistical process control (SPC) data in the etch, and deposition, and photolithography modules. Improve existing processes of record in the PIC wafer fab in terms of yield, cycle time, and manufacturability. Support the wafer fab engineering and operations teams to develop, control and optimize wafer fabrication processes.\n",
"ExternalContactEmail": null,
"ExternalPostedEndDate": null,
"OtherRequisitionTitle": null,
"requisitionFlexFields": [
{
"Value": "No",
"Prompt": "Will NSA/CAPS approval be required? (E.g., accessing a US Customer Network?)",
"ControlType": "SingleChoiceList",
"SequenceNumber": 5
},
{
"Value": "Individual contributor",
"Prompt": "Role Type",
"ControlType": null,
"SequenceNumber": 8
},
{
"Value": "US Salary range: $69,066.67 - $ 128,266.67 \n* Plus potential incentive/variable compensation for eligible roles",
"Prompt": "US/Canada Salary Range",
"ControlType": "TextArea",
"SequenceNumber": 12
}
],
"ApplyWhenNotPostedFlag": false,
"DomesticTravelRequired": null,
"ExternalDescriptionStr": "<p>In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The <strong>Network Infrastructure </strong>group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise</p>\n<p>Join <strong>Optical Networks division</strong>, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.</p>\n<p>Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. </p>",
"ObjectVerNumberProfile": null,
"PrimaryLocationCountry": "US",
"CorporateDescriptionStr": "<p class=\"MsoNormal\" style=\"margin-bottom:0cm;\"><b><span>Come create the technology that helps the world act together<br/> </span></b><span><br/> Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world.<br/> We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work<br/> <br/> <b>What we offer<br/> </b><span> </span><br/> Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered.<br/> <br/><b>Nokia is committed to inclusion and is an equal opportunity employer<br/> </b><br/> Nokia has received the following recognitions for its commitment to inclusion & equality:<br/></span></p>\n<ul>\n <li><span> One of the World’s Most Ethical Companies by Ethisphere</span></li>\n <li><span> Gender-Equality Index by Bloomberg</span></li>\n <li><span> Workplace Pride Global Benchmark</span></li>\n</ul>\n<p></p>At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect. <br/>Join us and be part of a company where you will feel included and empowered to succeed.<br/> <br/><b>Additional Information<br/> </b><br/> US/Canada Nokia Offers a comprehensive benefits package that includes but is not limited to:<br/> \n<p></p>\n<ul>\n <li><span> Corporate Retirement Savings Plan</span></li>\n <li><span> Health and dental benefits</span></li>\n <li><span> Short-term disability, and long-term disability</span></li>\n <li><span> Life insurance, and AD&D – Company paid 2x base pay</span></li>\n <li><span> Optional or Supplemental life and AD&D insurance (Employee/Spouse/Child)</span></li>\n <li><span> Paid time off for holidays and Vacation</span></li>\n <li><span> Employee Stock Purchase Plan</span></li>\n <li><span> Tuition Assistance Plan</span></li>\n <li><span> Adoption assistance</span></li>\n <li><span> Employee Assistance Program/Work Life Resource Program</span></li>\n</ul>\n<p></p>The above benefits exclude students. \n<p></p> <b>Disclaimer for US/Canada</b><br/> <br/> Nokia Maintains broad annual base salary ranges for its roles in order to account for variations in knowledge, skills, experience and market conditions, and with consideration to internal peer equity.(<u>Check the salary ranges in the job info section for this role</u>)<br/><br/> <b>All North America job posts will post for a minimum of 7 calendar days and up to 180 days or until candidate/s identified.</b>",
"ExternalPostedStartDate": "2026-05-05T00:32:10+00:00",
"ExternalQualificationsStr": "<div style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);color:rgb(51, 51, 51);font-family:";Helvetica Neue", Helvetica, Arial, sans-seriffont-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"><div style=\"box-sizing:border-box;margin-right:0px;width:928.997px;\"><div><div style=\"box-sizing:border-box;margin-right:0px;width:928.997px;\"><div style=\"white-space:normal;\"><ul><li>JMP, DOE, SPC and their application to semiconductor manufacturing</li><li>Working knowledge of semiconductor fabrication processes, and expertise in etch, deposition, photolithography and related processes. </li><li>Strong initiative, leadership and communication skills. </li><li>Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume. </li><li>Experience supporting a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution.</li></ul><p><br/><b>Education/Experience Required:</b> B.S degree or equivalent experience.</p><p> </p><p><b>Preferred Knowledge/Skills/Abilities:</b></p><ul><li>Technical depth in aspects of, etch, deposition, photolithography or similar tools and processes used for semiconductor manufacturing. 5 years’ experience in broad aspects of semiconductor wafer fabrication.</li><li>Knowledge of wafer fab metrology tools, for example ellipsometry, CD-SEM, step height, and overlay metrology</li><li>Clear communication of problems, challenges, and initiative in deploying solutions.</li><li>A working knowledge and fab experience from pathfinding through mature production. </li><li>A compound semiconductor background is a plus</li></ul></div></div></div></div></div><div style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);color:rgb(51, 51, 51);font-family:";Helvetica Neue", Helvetica, Arial, sans-seriffont-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"><div style=\"margin-top:15px;\"> </div></div><div style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);color:rgb(51, 51, 51);font-family:";Helvetica Neue", Helvetica, Arial, sans-seriffont-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"><div style=\"box-sizing:border-box;margin-right:0px;width:928.997px;\"><div><span style=\"background-color:transparent;color:rgb(112,112,112);font-family:-apple-system, BlinkMacSystemFont, ";Segoe UI", "Helvetica Neue", Arial, sans-seriffont-size:14px;\">Same Posting Description for Internal and External Candidates</span></div></div></div>",
"InternalQualificationsStr": "<div style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);color:rgb(51, 51, 51);font-family:";Helvetica Neue", Helvetica, Arial, sans-seriffont-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"><div style=\"box-sizing:border-box;margin-right:0px;width:928.997px;\"><div><div style=\"box-sizing:border-box;margin-right:0px;width:928.997px;\"><div style=\"white-space:normal;\"><ul><li>JMP, DOE, SPC and their application to semiconductor manufacturing</li><li>Working knowledge of semiconductor fabrication processes, and expertise in etch, deposition, photolithography and related processes. </li><li>Strong initiative, leadership and communication skills. </li><li>Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume. </li><li>Experience supporting a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution.</li></ul><p><br/><b>Education/Experience Required:</b> B.S degree or equivalent experience.</p><p> </p><p><b>Preferred Knowledge/Skills/Abilities:</b></p><ul><li>Technical depth in aspects of, etch, deposition, photolithography or similar tools and processes used for semiconductor manufacturing. 5 years’ experience in broad aspects of semiconductor wafer fabrication.</li><li>Knowledge of wafer fab metrology tools, for example ellipsometry, CD-SEM, step height, and overlay metrology</li><li>Clear communication of problems, challenges, and initiative in deploying solutions.</li><li>A working knowledge and fab experience from pathfinding through mature production. </li><li>A compound semiconductor background is a plus</li></ul></div></div></div></div></div><div style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);color:rgb(51, 51, 51);font-family:";Helvetica Neue", Helvetica, Arial, sans-seriffont-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"><div style=\"margin-top:15px;\"> </div></div><div style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);color:rgb(51, 51, 51);font-family:";Helvetica Neue", Helvetica, Arial, sans-seriffont-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"><div style=\"box-sizing:border-box;margin-right:0px;width:928.997px;\"><div><span style=\"background-color:transparent;color:rgb(112,112,112);font-family:-apple-system, BlinkMacSystemFont, ";Segoe UI", "Helvetica Neue", Arial, sans-seriffont-size:14px;\">Same Posting Description for Internal and External Candidates</span></div></div></div>",
"OrganizationDescriptionStr": "",
"primaryLocationCoordinates": [
{
"Latitude": "39.82844",
"Longitude": "-98.57939",
"CountryCode": "US",
"GeographyId": 300000000480126,
"GeographyNodeId": 100000448855450
}
],
"ExternalResponsibilitiesStr": "<ul><li>Optimize plasma deposition, plasma etch, wet etch and clean, and related processes needed for PIC wafer fabrication.</li><li>Work in teams to scale PIC wafer fabrication processes to larger wafer sizes, while meeting key objectives for PIC yield, uniformity, and end-of-line parametric performance.</li><li>Troubleshoot wafer fabrication process problems to enable a smooth flow of production and development wafers in the fab. Support engineering process and tool owners in resolving fab process or equipment problems.</li><li>Execute fabrication work and data collection to support process development for etch, and deposition, and photolithography roadmap activities needed for future PIC technology. </li><li>Utilize metrology equipment and test structures to maintain process control across wafer fab process modules, improve production yield and enable and guide new process development.</li></ul>",
"InternalResponsibilitiesStr": "<ul><li>Optimize plasma deposition, plasma etch, wet etch and clean, and related processes needed for PIC wafer fabrication.</li><li>Work in teams to scale PIC wafer fabrication processes to larger wafer sizes, while meeting key objectives for PIC yield, uniformity, and end-of-line parametric performance.</li><li>Troubleshoot wafer fabrication process problems to enable a smooth flow of production and development wafers in the fab. Support engineering process and tool owners in resolving fab process or equipment problems.</li><li>Execute fabrication work and data collection to support process development for etch, and deposition, and photolithography roadmap activities needed for future PIC technology. </li><li>Utilize metrology equipment and test structures to maintain process control across wafer fab process modules, improve production yield and enable and guide new process development.</li></ul>",
"InternationalTravelRequired": null
},
"list_job": {
"Id": "23288",
"Title": "Manufacturing Engineer – PIC wafer fabrication",
"JobType": null,
"Distance": 1777939200000,
"JobShift": null,
"Language": "US",
"WorkDays": null,
"JobFamily": null,
"Relevancy": 2,
"WorkHours": null,
"Department": null,
"HotJobFlag": false,
"PostedDate": "2026-05-05",
"StudyLevel": null,
"WorkerType": null,
"GeographyId": 300000000480126,
"JobFunction": null,
"JobSchedule": null,
"BusinessUnit": null,
"ContractType": null,
"ManagerLevel": null,
"Organization": null,
"TrendingFlag": true,
"workLocation": [
{
"Country": "US",
"Region1": null,
"Region2": "California",
"Region3": null,
"Building": null,
"Latitude": 37.4023,
"Longitude": -122.00764,
"LocationId": 300000892203459,
"PostalCode": "94089-1015",
"TownOrCity": "Sunnyvale",
"AddressLine1": "255 Caspian Drive",
"AddressLine2": null,
"AddressLine3": null,
"AddressLine4": null,
"LocationName": "Infinera Caspian Dr"
}
],
"LegalEmployer": null,
"MediaThumbURL": null,
"WorkplaceType": "",
"BusinessUnitId": 300000006664259,
"OrganizationId": 300000806573851,
"PostingEndDate": null,
"LegalEmployerId": 300001149319675,
"PrimaryLocation": "United States",
"WorkDurationYears": null,
"WorkplaceTypeCode": null,
"BeFirstToApplyFlag": false,
"WorkDurationMonths": null,
"otherWorkLocations": [],
"secondaryLocations": [],
"ShortDescriptionStr": "Support a balance of sustaining, optimization, and qualification of wafer fabrication processes, including etch, and deposition and photolithography. These processes are applied to both existing and new technology generations of Photonic Integrated Circuits (PICs). Participate in the development of wafer process recipes, operational procedures, and provide other support needed to qualify new tools needed for the release of an additional PIC wafer manufacturing site. Collect, interpret, and respond to wafer fab statistical process control (SPC) data in the etch, and deposition, and photolithography modules. Improve existing processes of record in the PIC wafer fab in terms of yield, cycle time, and manufacturability. Support the wafer fab engineering and operations teams to develop, control and optimize wafer fabrication processes.\n",
"requisitionFlexFields": [],
"DomesticTravelRequired": null,
"PrimaryLocationCountry": "US",
"ExternalQualificationsStr": null,
"ExternalResponsibilitiesStr": null,
"InternationalTravelRequired": null
},
"detail_meta": {
"url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmRestApi/resources/latest/recruitingCEJobRequisitionDetails?expand=all&onlyData=true&finder=ById;Id=%2223288%22,siteNumber=CX_1",
"http_status": 200,
"content_type": "application/json",
"response_bytes": 17494
},
"detail_errors": []
}Get this page with API
Rendered from the bluedoor Job Postings API. Reproduce it:
GET https://api.bluedoor.sh/job-postings/v1/jobs/a5c668254552cc817e006cbb10ec46231f2ea071?include=descriptionJSONGET https://api.bluedoor.sh/job-postings/v1/orgs/0229f528-a584-4e4f-9943-249cfaac294eJSONGET https://api.bluedoor.sh/job-postings/v1/sources/dbfc4c22-73ba-4fc5-9705-234e3e914c7cJSONGET https://api.bluedoor.sh/job-postings/v1/jobs/a5c668254552cc817e006cbb10ec46231f2ea071/eventsJSON