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Digital Design Engineer

Espace · Saratoga, CA · On Site · Active · $130,000–$225,000 / year · Lever

Job facts

Field	Value
Company	Espace
Title	Digital Design Engineer
Normalized title	-
Department / team	E-Space US / Engineering & Operations
Location	Saratoga, CA, United States
Work model	On Site
Employment type	Full Time
Salary	$130,000–$225,000 / year
Status	active
ATS provider	Lever
Posted / first seen	2026-04-02 / 2026-05-29
Changed / last seen	2026-05-29 / 2026-06-06

Related slices

Page	What it contains	Open
Company jobs	Active postings from Espace.	Open
Company breakdowns	Role, location, ATS, and work model facets for this company.	Open
ATS provider jobs	Active postings observed through Lever.	Open
Provider filtered search	The same provider as a filtered job collection.	Open
City jobs	Active postings in Saratoga.	Open
Department jobs	Active postings in E-Space US.	Open
Work model jobs	Active On Site postings.	Open
Lifecycle events	Open, update, close, and reopen events for this posting.	Open
Original posting	Canonical source or apply URL captured from the ATS.	Open

Linked records

Company	Espace
Source	0e4c8640-c166-4c81-94c1-78a80cc89393
ATS provider	Lever

Description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking experienced Digital Design Engineers to join our Satellite Avionics team. In this role you will own the electrical design of complex digital boards for a next-generation satellite constellation, including high-speed interfaces, FPGA integration, and mixed-signal subsystems. You will play a central role in delivering flight-qualified avionics hardware from concept through qualification. This is a full time, exempt position, based out of our Saratoga office. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Why E-Space is right for you: As a member of our team, you will play a crucial role in driving our success. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals. In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry. We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space: • An opportunity to really make a difference • Sustainability at our core • Fair and honest workplace • Innovative thinking is encouraged • Competitive salaries • Continuous learning and development • Health and wellness care options • Financial solutions for the future • Optional legal services (US only) • Paid holidays • Paid time off Key Responsibilities: Own schematic design and component selection for digital avionics boards, from concept through flight qualification. Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces with proper timing closure. Develop clocking architectures including PLL configuration, jitter management, and clock distribution networks. Perform power budgeting and system-level power allocation across board subsystems. Apply radiation-tolerant design techniques including SEU/SEE mitigation, TID considerations, and appropriate component derating. Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout requirements. Drive board bring-up activities including configuration, interface verification, and structured debugging. Participate in design reviews and cross-functional integration with RF, power, thermal, and mechanical teams. Required Qualifications: Own schematic design and component selection for digital avionics boards, from concept through flight qualification. Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces with proper timing closure. Develop clocking architectures including PLL configuration, jitter management, and clock distribution networks. Perform power budgeting and system-level power allocation across board subsystems. Apply radiation-tolerant design techniques including SEU/SEE mitigation, TID considerations, and appropriate component derating. Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout requirements. Drive board bring-up activities including configuration, interface verification, and structured debugging. Participate in design reviews and cross-functional integration with RF, power, thermal, and mechanical teams. Preferred Qualifications: Experience with satellite or spacecraft avionics design and qualification (EM/QM/FM build cycles). Background in non-volatile memory technologies (Flash, MRAM, FRAM) and in-system programmability. Exposure to power supply design and power integrity analysis for digital boards. Experience with design for radiation reliability and single-event effects mitigation at the board level. Familiarity with signal integrity simulation tools (HyperLynx SI/PI, Ansys, ADS). Tools & Technologies: Altium Designer (schematic capture and layout review) HyperLynx SI, SI/PI, and Full-Wave (signal and power integrity) SPICE-based circuit simulation FPGA vendor toolchains (for interface bring-up and debug)

Full job record

Job ID	a2abff79353afeb11246bb2d9155e2334429f7c6
Org ID	e990e975-83d3-4663-9e17-f465a630f542
Source ID	0e4c8640-c166-4c81-94c1-78a80cc89393
Board ID	0e4c8640-c166-4c81-94c1-78a80cc89393
Provider	lever
Provider Job Key	690e923d-a9cc-475d-b2fd-1dbdef759e27
Title	Digital Design Engineer
Normalized Title	—
Status	active
Active	yes
Location Text	Saratoga, CA
Department	E-Space US
Team	Engineering & Operations
Employment Type	Full-Time
Workplace Type	on_site
Remote Policy	—
Country	United States
Region	CA
City	Saratoga
Salary Raw	USD 130000-225000 per-year-salary
Salary Min	130,000
Salary Max	225,000
Salary Currency	USD
Salary Period	year
Source URL	https://jobs.lever.co/espace/690e923d-a9cc-475d-b2fd-1dbdef759e27
Apply URL	https://jobs.lever.co/espace/690e923d-a9cc-475d-b2fd-1dbdef759e27/apply
First Seen At	2026-05-29 07:07:40Z
Last Seen At	2026-06-06 19:12:13Z
Last Checked At	2026-06-06 19:12:13Z
Last Changed At	2026-05-29 07:07:40Z
Inactive At	—
Source Posted At	2026-04-02 21:24:05Z
Source Updated At	—
Raw Payload Uri	s3://job-postings-prod-raw-590183727216/raw/provider=lever/board=espace/date=2026-06-06/2026-06-06T19-12-11-686Z-efb9c8f38a20ecf78d9a90ab2968642b4db6ac83147e0e9af0d4e6ee8081f10b.json

Event Fields

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Parsed Structured

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Extensions

{}

Native Structured

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