ASIC Architect

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      "role": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Position Overview</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">We are looking for a highly experienced ASIC Architect&nbsp;to contribute to the definition and implementation of Eridu's industry leading networking products. This is a unique opportunity to help shape the future of AI Networking.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Responsibilities&nbsp;</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Collaborate with chip and system microarchitects to align ASIC architecture with system-level goals for throughput, latency, and power efficiency.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Guide modeling and feasibility analysis of packet flow behavior through the switch datapath to validate architectural choices, including throughput, latency, power and area efficiencies.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design implementation and handoff.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Guide integration of internal and external IPs (e.g. MAC, PCIe, SerDes) into the broader architecture. Drive interface requirements.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Participate in design reviews, performance modeling, test and verification strategies and architectural trade-off analysis.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Contribute to post-silicon validation for performance and correctness. </span><span style=\"color:windowtext;white-space:pre-wrap;\">Investigate and resolve complex issues related to ASIC data path, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Qualifications</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">MSEE with </span><b><strong style=\"white-space:pre-wrap;\">10+ years of experience</strong></b><span style=\"white-space:pre-wrap;\">, preferably in networking ASIC architecture and design.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Candidates with experience in related areas of computer and parallel processing architectures – in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths &nbsp;– are also highly desired.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Capability to develop Architecture behavioral models is highly desired.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience working across the ASIC development lifecycle, from concept through productization.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience in high-speed I/O integration&nbsp;(e.g., PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable.</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power).</span></li><li style=\"color:black;font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex issues</span><span style=\"white-space:pre-wrap;\">. Exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:18pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"color:black;font-size:18pt;white-space:pre-wrap;\">Why Join Us?</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Notice to Recruiting Agencies</strong></b></h6><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.</span></p>",
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