Principal Silicon Validation Engineer, SerDes/PAM4

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. Basic Qualifications: Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred. 8 + years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! Proven track record solving problems independently, executing validation plans for complex SoC designs. Required Experience: Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet. Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4 Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis. Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA Preferred Experience: Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding Familiarity with PCIe standards and both NRZ and PAM-4 signaling Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

{
  "content_hash": "55d1b221b198b1b4484d508e593bcd70b71bf38fbfb5ecaf38ee716ab0b75738",
  "source_hash": "6ba32780f52e3a9f0fde5e8a21c1f4c1d74a9c46c28eddbc180d9191115d4aaf",
  "last_changed_at": "2026-06-06T07:35:38.727Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "San Jose, California, United States",
    "city": "San Jose",
    "region": "CA",
    "country": "United States",
    "is_remote": false,
    "confidence": 0.95
  },
  "salary_max": 230000,
  "salary_min": 185000,
  "inferred_at": "2026-06-06T07:35:38.685Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en",
    "location": {
      "raw": "San Jose, California, United States",
      "city": "San Jose",
      "region": "CA",
      "country": "United States",
      "is_remote": false,
      "confidence": 0.95
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": "year",
  "workplace_type": null,
  "salary_currency": "USD"
}

{}

{
  "title": "Principal Silicon Validation Engineer, SerDes/PAM4",
  "offices": [
    {
      "id": 4000118005,
      "name": "San Jose",
      "location": "San Jose, United States",
      "child_ids": [],
      "parent_id": 4019546005
    }
  ],
  "language": "en",
  "location": {
    "name": "San Jose, California, United States"
  },
  "metadata": [
    {
      "id": 12122734005,
      "name": "Country",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 12122790005,
      "name": "City",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 7826080005,
      "name": "Job Family/Domain",
      "value": "Hardware Engineering",
      "value_type": "single_select"
    },
    {
      "id": 7826085005,
      "name": "Role Type",
      "value": "Experienced",
      "value_type": "single_select"
    }
  ],
  "updated_at": "2026-06-05T13:07:16-04:00",
  "departments": [
    {
      "id": 4025526005,
      "name": "Hardware Engineering",
      "child_ids": [],
      "parent_id": 4000196005
    }
  ],
  "company_name": "Astera Labs",
  "requisition_id": 4419978005,
  "first_published": "2026-02-18T17:01:14-05:00",
  "application_deadline": null
}