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Lead FPGA Engineer

Astrolab · Hawthorne, California, Hawthorne, CA · On Site · Active · $183,000–$230,000 / year · Pinpoint

Job facts

FieldValue
CompanyAstrolab
TitleLead FPGA Engineer
Normalized title-
Department / teamAvionics
LocationHawthorne, CA, United States
Work modelOn Site
Employment typeFull Time
Salary$183,000–$230,000 / year
Statusactive
ATS providerPinpoint
Posted / first seen / 2026-05-31
Changed / last seen2026-05-31 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Astrolab.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Pinpoint.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Hawthorne.Open
Department jobsActive postings in Avionics.Open
Work model jobsActive On Site postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyAstrolab
Source79cbb30c-0051-49e6-9194-94bbe06b977d
ATS providerPinpoint

Description

Venturi Astrolab, Inc. (Astrolab) is pioneering new ways to explore and operate on distant planetary bodies. We are singularly focused on designing, building, and operating a fleet of multi-purpose commercial planetary rovers to extend and enhance humanity’s presence in the solar system. We are seeking motivated, creative, and exceptional people to join our world-class team. The Avionics team is responsible for all aspects of the electrical systems and hardware on Astrolab’s electric rover vehicles and ground support equipment. We work collaboratively with all teams at Astrolab to provide exceptionally capable and reliable electronics to serve our missions. The Lead FPGA Engineer will lead the FPGA Engineering group and participate in all aspects of the development and test of Avionics FPGA RTL designs for Astrolab rovers. The ideal candidate has 10+ years of experience in FPGA firmware development including RTL design, simulations, analysis, verification, and HW testing. This position will report to the Director of Avionics Engineering and will be based in our Hawthorne, CA office. Own and define the vehicle system FPGA related architectures, standards, practices, processes, tools, etc. Develop system digital computing architectures and requirements in collaboration with other engineering disciplines including defining HW/SW interfaces between fabric logic and processing subsystems. Lead the FPGA Engineering team of 3+ people in the development and delivery of Astrolab FPGA RTL design and verification. Support FPGA Engineering direct reports through their technical work, performance evaluations, and career growth. Own unit level RTL development from blank sheet to flight for Microsemi, Xilinx, or other FPGA or SoC devices in either Verilog or VHDL. Perform design verification including simulations, test benches, timing analysis, and hardware testing. Lead design reviews, demonstrate requirement traceability, and create documentation for FPGA operation and interfacing with other SW and FPGA systems. Lead and participate in test campaigns ranging from unit level manual tests, unit automated tests, and system level tests. Bachelor of Science degree in Computer Engineering, Electrical Engineering, or equivalent. 10+ years of experience in FPGA RTL architecture, development, verification, deployment, and maintenance. 2+ years of team leadership experience as manager of direct reports. Skilled at Verilog or VHDL. Skilled in at least 1 scripting language (TCL, shell, Python, etc). Skilled in verification techniques, and timing/stability analysis. Proficiency in understanding PCB designs and reading schematics. Proficiency in understanding embedded software. Proficiency with AXI protocols (at least AXI4 family). Knowledge of common bus and memory interfaces (DDR4, SPI, I2C, UART, etc). Demonstrated success working in a dynamic environment. Additional Responsibilities Design for space environments including radiation impacts and mitigations. Join a team of best-in-class engineers building the foundation of planetary surface exploration Equity ownership in the company Comprehensive health benefits, including medical, dental, vision, and mental health support 401(k) plan with company match Flexible PTO and parental leave Home office set up reimbursement Fully flexible and remote friendly work environment Weekly lunch stipend, plus complimentary snacks and beverages on-site Once a month social hour on-site with food and drinks

Full job record

Job ID9e978674f9b52d39751ad254f385f32d6d3e1d98
Org ID55f9f511-162b-4c3b-a31b-845037552aab
Source ID79cbb30c-0051-49e6-9194-94bbe06b977d
Board ID79cbb30c-0051-49e6-9194-94bbe06b977d
Providerpinpoint
Provider Job Key462698
TitleLead FPGA Engineer
Normalized Title
Statusactive
Activeyes
Location TextHawthorne, California, Hawthorne, CA
DepartmentAvionics
Team
Employment Typefull_time
Workplace Typeon_site
Remote Policy
CountryUnited States
RegionCA
CityHawthorne
Salary Raw$183,000 - $230,000 / year
Salary Min183,000
Salary Max230,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://astrolab.pinpointhq.com/en/postings/f2a6fff9-37a7-4b4b-b595-84256e04cc61
Apply URLhttps://astrolab.pinpointhq.com/en/postings/f2a6fff9-37a7-4b4b-b595-84256e04cc61
First Seen At2026-05-31 17:46:08Z
Last Seen At2026-06-06 10:52:14Z
Last Checked At2026-06-06 10:52:14Z
Last Changed At2026-05-31 17:46:08Z
Inactive At
Source Posted At
Source Updated At
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=pinpoint/board=astrolab/date=2026-06-06/2026-06-06T10-52-13-428Z-39071ea0baf71351bbbfe0a77eac3ce32ecf017d17f9cb1459e1609c77595d90.json
Event Fields
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  "last_changed_at": "2026-05-31T17:46:08.101Z",
  "active_status": "active"
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Parsed Structured
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Extensions
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Native Structured
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  "title": "Lead FPGA Engineer",
  "benefits": "<ul><li><!--block-->Join a team of best-in-class engineers building the foundation of planetary surface exploration</li><li><!--block-->Equity ownership in the company</li><li><!--block-->Comprehensive health benefits, including medical, dental, vision, and mental health support</li><li><!--block-->401(k) plan with company match</li><li><!--block-->Flexible PTO and parental leave</li><li><!--block-->Home office set up reimbursement</li><li><!--block-->Fully flexible and remote friendly work environment</li><li><!--block-->Weekly lunch stipend, plus complimentary snacks and beverages on-site</li><li><!--block-->Once a month social hour on-site with food and drinks</li></ul>",
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  "description": "<div><!--block-->Venturi Astrolab, Inc. (Astrolab) is pioneering new ways to explore and operate on distant planetary bodies. We are singularly focused on designing, building, and operating a fleet of multi-purpose commercial planetary rovers to extend and enhance humanity’s presence in the solar system. We are seeking motivated, creative, and exceptional people to join our world-class team.&nbsp; &nbsp;&nbsp;<br><br></div><div><!--block-->The Avionics team is responsible for all aspects of the electrical systems and hardware on Astrolab’s electric rover vehicles and ground support equipment.&nbsp; We work collaboratively with all teams at Astrolab to provide exceptionally capable and reliable electronics to serve our missions.&nbsp; &nbsp;<br><br></div><div><!--block-->The Lead FPGA Engineer will lead the FPGA Engineering group and participate in all aspects of the development and test of Avionics FPGA RTL designs for Astrolab rovers. The ideal candidate has 10+ years of experience in FPGA firmware development including RTL design, simulations, analysis, verification, and HW testing.<br><br></div><div><!--block--><strong>This position will report to the Director of Avionics Engineering and will be based in our Hawthorne, CA office.&nbsp;</strong></div>",
  "compensation": "$183,000 - $230,000 / year",
  "reporting_to": "Jake Peery",
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  "compensation_currency": "USD",
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  "skills_knowledge_expertise": "<ul><li><!--block-->Bachelor of Science degree in Computer Engineering, Electrical Engineering, or equivalent.&nbsp;</li><li><!--block-->10+ years of experience in FPGA RTL architecture, development, verification, deployment, and maintenance.&nbsp;</li><li><!--block-->2+ years of team leadership experience as manager of direct reports.&nbsp;</li><li><!--block-->Skilled at Verilog or VHDL.&nbsp;</li><li><!--block-->Skilled in at least 1 scripting language (TCL, shell, Python, etc).&nbsp;</li><li><!--block-->Skilled in verification techniques, and timing/stability analysis.&nbsp;</li><li><!--block-->Proficiency in understanding PCB designs and reading schematics.&nbsp;</li><li><!--block-->Proficiency in understanding embedded software.&nbsp;</li><li><!--block-->Proficiency with AXI protocols (at least AXI4 family).&nbsp;</li><li><!--block-->Knowledge of common bus and memory interfaces (DDR4, SPI, I2C, UART, etc).&nbsp;</li><li><!--block-->Demonstrated success working in a dynamic environment.&nbsp;</li></ul><div><!--block--><strong>Additional Responsibilities</strong>&nbsp;</div><ul><li><!--block-->Design for space environments including radiation impacts and mitigations.&nbsp;</li></ul>",
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