PCIe ASIC Design Engineer

{
  "content_hash": "6f234ff248c8fc9537371ad98a3730ca955b59a977544b0906d4bd011a718a57",
  "source_hash": "cbe0b6ae447f207d0883b05f0bd76a55616262f90000883fda878fb28c751671",
  "last_changed_at": "2026-05-30T06:07:46.604Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "San Jose, California, United States",
    "city": "San Jose",
    "region": "CA",
    "country": "United States",
    "is_remote": true,
    "confidence": 0.8
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-06T10:29:01.185Z",
  "launch_scope": {
    "reason": "bamboohr_production_catalog",
    "included": true,
    "location": {
      "raw": "San Jose, California, United States",
      "city": "San Jose",
      "region": "CA",
      "country": "United States",
      "is_remote": true,
      "confidence": 0.8
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": "remote",
  "salary_period": null,
  "workplace_type": "remote",
  "salary_currency": null
}

{}

{
  "list_job": {
    "id": "125",
    "isRemote": null,
    "location": {
      "city": null,
      "state": null
    },
    "atsLocation": {
      "city": "San Jose",
      "state": "California",
      "country": "United States",
      "province": null
    },
    "departmentId": "18609",
    "locationType": "1",
    "jobOpeningName": "PCIe ASIC Design Engineer",
    "departmentLabel": "ASIC Engineering",
    "employmentStatusLabel": "Full-Time (U.S. Benefit Eligible)"
  },
  "detail_errors": [],
  "detail_job_opening": {
    "location": {
      "city": null,
      "state": null,
      "postalCode": null,
      "addressCountry": null
    },
    "datePosted": "2025-05-21",
    "atsLocation": {
      "city": "San Jose",
      "state": "California",
      "country": "United States",
      "countryId": "1"
    },
    "description": "<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\">At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.</span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><br>Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI &amp; HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.  </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"> </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\">We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. </span></p>\n<p><br></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Cornelis Networks is hiring </span><span>a </span><span>S</span><span>enior</span><span> ASIC Design Engineer </span><span>to lead the </span><span>design and </span><span>integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep </span><span>expertise</span><span> in PCI Express </span><span>protocol </span><span>(Gen4/Gen5/Gen6)</span><span>, integration into high performance ASICs, </span><span>emulation</span><span> and post silicon </span><span>bring</span><span>-</span><span>up.</span></span><span> </span></span></p>\n<p><br></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt; font-weight: bold\">Key Responsibilities: </span></p>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Own end-to-end integration of PCIe IP into complex ASIC designs.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Debug functional and performance issues at RTL, gate-level, and silicon.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Ensure compliance with PCIe specifications and </span><span>participate</span><span> in interoperability testing where needed.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Provide mentorship to junior engineers and help define PCIe subsystem development best practices.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Good understanding of</span><span> high-bandwidth, low-latency connectivity for high-performance </span><span>compute</span><span> platforms</span></span><span> </span></span></li>\n</ul>\n<p><br></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt; font-weight: bold\">Minimum Qualifications: </span></p>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>BS/MS in Electrical Engineering, Computer Engineering, or related field.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>10</span><span>+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Proven experience in silicon bring-up and </span><span>debug</span><span> of high-speed interfaces.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Strong scripting (Python, Perl, TCL) and debugging skills.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Strong verbal and written communication skills.</span></span><span> </span></span></li>\n</ul>\n<p><br></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt; font-weight: bold\">Preferred Qualifications: </span></p>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Experience with PCIe Gen5/Gen6 and advanced </span><span>retimer</span><span> or switch solutions.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Exposure to CXL, CCIX, or other cache-coherent interconnects.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Background in data center or AI/ML accelerator architectures.</span></span><span> </span></span></li>\n</ul>\n<ul>\n<li><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span><span>Experience with emulation </span><span>and prototyping</span><span> platforms (e.g., </span><span>ZeBu</span><span>, Palladium</span><span>, HAPS</span><span>) for PCIe subsystem validation.</span></span><span> </span></span></li>\n</ul>\n<p><br></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Location:</span> This is a remote position for employees residing within the United States.</span></p>\n<p><br></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\">We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"> </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\">At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"> </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\">In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\"> </span></p>\n<p><span style=\"color: rgb(0, 0, 0); font-family: Inter, sans-serif; font-size: 12pt\">Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></p>",
    "compensation": null,
    "departmentId": "18609",
    "locationType": "1",
    "seekPromoted": false,
    "jobCategoryId": null,
    "jobOpeningName": "PCIe ASIC Design Engineer",
    "departmentLabel": "ASIC Engineering",
    "jobOpeningStatus": "Open",
    "minimumExperience": null,
    "jobOpeningShareUrl": "https://cornelisnetworks.bamboohr.com/careers/125",
    "employmentStatusLabel": "Full-Time (U.S. Benefit Eligible)"
  }
}