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Principal Analog Mixed-Signal Design Engineer

555e77b2 029a 4357 8712 1dd910b41621 19000101 000001 · Santa Clara, CA, US, Santa Clara, CA · Active · $164,800–$226,600 / year · ADP Workforce Now Recruiting

Job facts

FieldValue
Company555e77b2 029a 4357 8712 1dd910b41621 19000101 000001
TitlePrincipal Analog Mixed-Signal Design Engineer
Normalized title-
Department / team-
LocationSanta Clara, CA, United States
Work model-
Employment typeFull Time
Salary$164,800–$226,600 / year
Statusactive
ATS providerADP Workforce Now Recruiting
Posted / first seen2026-01-27 / 2026-05-31
Changed / last seen2026-06-20 / 2026-06-20

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Company555e77b2 029a 4357 8712 1dd910b41621 19000101 000001
Sourcec2707813-bcf1-47e7-bd8f-33621286a357
ATS providerADP Workforce Now Recruiting

Description

About SiTime SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com . Responsibilities: Lead development of analog Mixed-signal IC and owns the top level Supervise and review block designer work and hold design review Work with cross-functional team to architect the chip for DFT Closely work and support cross functional team for bench validation, qualification and final test development. Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications Perform transistor-level design and simulation using industry leading EDA tools Lead comprehensive design reviews Supervise Analog Circuit Physical Design Layout and edit layouts Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release Work closely with the verification team to define the verification matrix. Have the ownership of the top-level schematic and run all the top-level analog simulation. Participate in top-level AMS verification. Qualifications & Requirements : M.Sc. with minimum 10 years of relevant experience or Ph.D. with 6 years of with relevant experience in Electrical Engineering Provel track record of taking at least one analog-mixed signal part to high-volume production. Proven track record at each stage of the following: Circuit architecture development and technical feasibility studies Writing detailed block-level specifications and review documents Detailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture. Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers Extensive experience with post-layout extraction and verifications Experience with validation, characterization, qualification, and adherence to production release criteria Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers Ability to work independently and drive solutions to challenging problems Desired Characteristics & Attributes: Strong team player Compensation Range: At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. The annual base salary range for this role is $164,800.00 – $226,600.00. The final offer is determined by factors such as location, experience, education, and training. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success. Benefits offered : 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans. SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program. Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. Innovation on Top – Philosophies of Innovation with Rajesh Vashist Fabrication Knowledge – An Interview with Rajesh Vashist SiTime Corporation – YouTube #LI-SITIME

Full job record

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Source IDc2707813-bcf1-47e7-bd8f-33621286a357
Board IDc2707813-bcf1-47e7-bd8f-33621286a357
Provideradp_workforcenow
Provider Job Key582643
TitlePrincipal Analog Mixed-Signal Design Engineer
Normalized Title—
Statusactive
Activeyes
Location TextSanta Clara, CA, US, Santa Clara, CA
Department—
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Employment Typefull_time
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CountryUnited States
RegionCA
CitySanta Clara
Salary Rawsalary range for this role is $164,800.00 – $226,600
Salary Min164,800
Salary Max226,600
Salary CurrencyUSD
Salary Periodyear
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First Seen At2026-05-31 18:53:32Z
Last Seen At2026-06-20 14:28:20Z
Last Checked At2026-06-20 14:28:20Z
Last Changed At2026-06-20 14:28:20Z
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Source Posted At2026-01-27 18:29:00Z
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    "requisitionDescription": "<div><div><div><div><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;' data-pasted=\"true\"><strong><span style=\"font-family: arial, sans-serif; font-size: 18px;\">About SiTime</span></strong></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;' data-pasted=\"true\"><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">SiTime is the Precision Timing company.&nbsp;</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit:&nbsp;</span><span style=\"font-size: 18px; font-family: arial, sans-serif;\">&nbsp;<a href=\"https://www.globenewswire.com/Tracker?data=KZboO_E5KYNf2nXu9snYUrujcxPVV14r8VUqaw-krQjviK4SVzg-T3gX0Yv8pdrIU2yKG5VITW08WA-AWCTQKQ==\" target=\"_blank\" style=\"font-family: arial,sans-serif;\">www.sitime.com</a>.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><br></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>Responsibilities:</strong></span></p><div style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><ul style=\"margin-bottom:0in;list-style-type: disc;\"><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Lead development of analog Mixed-signal IC and owns the top level</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Supervise and review block designer work and hold design review</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Work with cross-functional team to architect the chip for DFT&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Closely work and support cross functional team for bench validation, qualification and final test development.&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Perform transistor-level design and simulation using industry leading EDA tools&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Lead comprehensive design reviews&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Supervise Analog Circuit Physical Design Layout and edit layouts&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Work closely with the verification team to define the verification matrix.&nbsp;</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Have the ownership of the top-level schematic and run all the top-level analog simulation.</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Participate in top-level AMS verification. &nbsp;&nbsp;</li></ul></div><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-left:.5in;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>Qualifications &amp; Requirements : &nbsp;&nbsp;</strong><br></span></p><div style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><ul><li style=\"font-size: 18px; font-family: arial, sans-serif;\">M.Sc. with minimum 10 years of relevant experience or Ph.D. with 6 years of &nbsp;with relevant experience in Electrical Engineering&nbsp;</li><li style=\"font-size: 18px; font-family: arial, sans-serif;\">Provel track record of taking at least one analog-mixed signal part to high-volume production.</li><li style=\"font-size: 18px; font-family: arial, sans-serif;\">Proven track record at each stage of the following:<ul style=\"font-size: initial; font-family: initial;\"><li style=\"font-size: 18px; font-family: arial, sans-serif;\">Circuit architecture development and technical feasibility studies&nbsp;</li><li style=\"font-size: 18px; font-family: arial, sans-serif;\">Writing detailed block-level specifications and review documents&nbsp;</li></ul></li></ul></div><ul style=\"margin-bottom: 0in;list-style-type: disc;\"><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">Detailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture.<ul style=\"margin-bottom: 0in; list-style-type: disc; font-size: initial; font-family: initial;\"><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL&nbsp;</li><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers&nbsp;</li><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">Extensive experience with post-layout extraction and verifications&nbsp;</li><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">Experience with validation, characterization, qualification, and adherence to production release criteria&nbsp;</li><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers&nbsp;</li><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">Ability to work independently and drive solutions to challenging problems&nbsp;</li></ul></li></ul><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>Desired Characteristics &amp; Attributes:</strong></span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif; text-align: justify;\">Strong team player</li></ul><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;' data-pasted=\"true\"><strong><span style=\"font-family: arial, sans-serif; font-size: 18px;\">Compensation Range:</span></strong></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\">At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.&nbsp;</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\">The annual base salary range for this role is $164,800.00 &ndash; $226,600.00. The final offer is determined by factors such as location, experience, education, and training.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br>&nbsp;In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals&mdash;reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company&rsquo;s future growth and success.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong>Benefits offered</strong></span><span style=\"font-family: arial, sans-serif; font-size: 18px;\">: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"font-family: arial, sans-serif; color: black; background: white; font-size: 18px;\">SiTime is an&nbsp;</span><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><a href=\"http://www.sitime.com/images/EEO-is-the-law.pdf\" target=\"_blank\" style=\"font-family: arial,sans-serif;\"><span style=\"color: blue; background: white;\">Equal Opportunity Employer</span></a></span><span style=\"font-family: arial, sans-serif; color: black; background: white; font-size: 18px;\">. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.&nbsp;</span><span style=\"font-family: arial, sans-serif; font-size: 18px;\">SiTime participates in the&nbsp;</span><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><a href=\"http://www.sitime.com/images/E-Verify-Participation-Poster.pdf\" target=\"_blank\" style=\"font-family: arial,sans-serif;\"><span style=\"color: blue;\">E-Verify</span></a>&nbsp;</span><span style=\"font-family: arial, sans-serif; font-size: 18px;\">program.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><strong><span style=\"color: black;\">Learn More about SiTime:&nbsp;</span></strong></span><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">Review the&nbsp;</span><span style=\"font-size: 18px; font-family: arial, sans-serif;\"><a href=\"https://www.sitime.com/company/careers\" target=\"_blank\" style=\"font-family: arial,sans-serif;\">Get to Know SiTime</a></span><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">&nbsp;section of our career page to explore our culture, values, and what makes us unique.&nbsp;</span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in 0in 11.25pt; font-size: 18px; font-family: arial, sans-serif; color: black; text-align: justify;\"><span style=\"color: windowtext;\"><a href=\"https://www.innovatorsontap.com/podcast/the-philosophy-of-innovation-w-rajesh-vashist\" target=\"_blank\" style=\"font-size: 18px; font-family: arial, sans-serif;\">Innovation on Top &ndash; Philosophies of Innovation with Rajesh Vashist</a></span></li><li style=\"margin: 0in 0in 11.25pt; font-size: 18px; font-family: arial, sans-serif; color: black; text-align: justify;\"><span style=\"color: windowtext;\"><a href=\"https://www.fabricatedknowledge.com/p/an-interview-with-rajesh-vashist-3e0#details\" target=\"_blank\" style=\"font-size: 18px; font-family: arial, sans-serif;\">Fabrication Knowledge &ndash; An Interview with Rajesh Vashist</a></span></li><li style=\"margin: 0in 0in 11.25pt; font-size: 18px; font-family: arial, sans-serif; color: black; text-align: justify;\"><span style=\"color:windowtext;\"><a href=\"https://www.youtube.com/user/sitimecorp/videos\" target=\"_blank\" style=\"font-size: 18px; font-family: arial, sans-serif;\">SiTime Corporation &ndash; YouTube</a></span></li></ul><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-bottom:11.25pt;text-align:justify;'><br></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"font-family: arial, sans-serif; color: rgb(255, 255, 255); font-size: 18px;\">&nbsp;#LI-SITIME</span></p></div></div></div></div>\n",
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