Senior Signal/Power Integrity Engineer

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0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">What you'll do</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Collaborate with multi-disciplinary engineers (EE, System and Package) to define electrical performance related to SI, PI, EMI and EMC</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:10.5pt;white-space:pre-wrap;\">D</span><span style=\"white-space:pre-wrap;\">evelop engineering test plans and methodologies for SI and PI simulation, including modelling of power networks, parasitic, impedance-controlled transmission lines, vias, connectors, sockets, and system components.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Validate power and signal integrity in laboratory settings, ensuring alignment with design specifications and simulation outcomes.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Analyze simulation and lab data to identify design issues and propose corrective actions.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Ability to support multiple projects concurrently, ensuring timely completion of design and validation tasks.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Required 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design in of complex SoCs, PMICs, mixed-signal analog/digital designs for sensors and high-speed interfaces such as LPDDR4/4x, MIPI, 10G Ethernet and PCIe Gen 2/3</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience with system-level timing, loss budget including silicon, package and board impairments</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience with lab measurements, debugging, and SI correlations using oscilloscopes, spectrum analyzer, VNA and TDR</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Fluent in English communication, able to collaborate with teammates in different time zones</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Ability to travel internationally as needed</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Maintain company confidential information are a must&nbsp;</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;white-space:pre-wrap;\">&nbsp;</span><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Preferred Qualifications</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Master’s degree with more experience is highly desired</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Proactive member of the multi-disciplinary team, takes ownership of technical challenges and work with others to resolve issues</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Nice to have experience in substrate design and packaging technology</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Familiar with some of the device packaging processes such as die attach, flip chip, and wire bonding.</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Data analysis experience such as JMPs is a plus; Excel is OK.</span></li><li style=\"color:black;font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Programming and software maintenance skills are desired e.g. python, or C++</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:left;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Benefits </strong></b><span style=\"font-size:12pt;white-space:pre-wrap;\">(subject to location and local regulations)</span></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Competitive salary and equity&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Comprehensive medical, dental, and vision coverage&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">401(k) retirement plan&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Flexible vacation and time-off policy&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Collaborative, fast-paced, and inclusive work environment&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Opportunity to work on&nbsp;cutting-edge&nbsp;technologies with a highly cross-functional team&nbsp;</span></li></ul>",
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