Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions

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    "description": "<h2>Basic Qualifications </h2>\n<p>Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.</p>\n<p> </p>\n<p><strong>CLEARANCE REQUIREMENTS:</strong> Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.</p>\n<h2>Responsibilities for this Position</h2>\n<h2>What You'll Do</h2>\n<ul>\n <li>Architect and implement high-performance FPGA designs in VHDL and/or Verilog targeting Xilinx and Microchip device families.</li>\n <li>Perform synthesis, place-and-route, and timing closure using Vivado or Libero, including advanced techniques such as pipelining, register retiming, floorplanning, and physical optimization</li>\n <li>Develop and execute block-level simulations using QuestaSim/ModelSim with code coverage analysis (statement, branch, condition, expression)</li>\n <li>Create self-checking testbenches for correctness verification</li>\n <li>Design high-speed interfaces for inter-module communication and system integration</li>\n <li>Collaborate with systems engineers, software developers, and verification engineers in an Agile development environment</li>\n <li>Participate in design reviews, peer code reviews, and documentation of design specifications and interface control documents</li>\n <li>Contribute to CI/CD pipeline development for automated synthesis, simulation regression, and coverage tracking</li>\n <li>Support integration and lab bring-up activities, including on-target FPGA debug using ILAs and JTAG-based tools</li>\n</ul>\n<h2>Required Qualifications</h2>\n<ul>\n <li>Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design</li>\n <li>Hands-on experience with Xilinx Vivado Design Suite or Microchip Libero for synthesis, implementation, and timing analysis</li>\n <li>Experience targeting Xilinx and Microchip device families</li>\n <li>Ability to achieve timing closure on designs at 300+ MHz clock rates</li>\n <li>Experience with FPGA simulation tools (QuestaSim or ModelSim)</li>\n <li>Proficiency in writing self-checking testbenches with automated pass/fail determination</li>\n <li>Understanding of high-speed digital design principles: pipelining, clock domain crossing (CDC), metastability mitigation, and synchronous design</li>\n <li>Experience with AXI-Stream, AXI4, or similar on-chip bus protocols</li>\n <li>Ability to read and interpret timing reports, utilization summaries, and critical-path analysis output</li>\n <li>Strong written and verbal communication skills for design documentation and technical presentations</li>\n <li>S. Citizenship and ability to obtain/maintain a Secret security clearance</li>\n</ul>\n<h2>Preferred Qualifications</h2>\n<ul>\n <li>Experience with cryptographic algorithm implementation in hardware (AES, GCM, SHA, ECC, RSA, or similar)</li>\n <li>Experience with high-speed serial interfaces: PCIe, Ethernet (10G/25G/100G), Fibre Channel, Aurora, or GTY/GTM transceivers</li>\n <li>Experience with CI/CD pipelines for FPGA development (GitLab CI) including automated synthesis and regression testing</li>\n <li>Proficiency in scripting languages (Tcl, Python, Bash) for build automation and design flow scripting</li>\n <li>Experience with version control systems (GitLab) and collaborative development workflows</li>\n <li>Experience with Xilinx IP cores: FIFO Generator, Clock Wizard, MIG/DDR controllers, DMA/Bridge subsystems</li>\n <li>Experience with embedded processors in FPGA (MicroBlaze, Zynq PS, Versal AI Engine)</li>\n</ul>\n<p> </p>\n<p>#CJ3</p>\n<h2>Salary Note</h2>This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.\n<h2>Combined Salary Range</h2>USD $135,396.00 - USD $150,205.00 /Yr.\n<h2>Company Overview</h2>\n<p>General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!</p>\n<p>Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans</p>",
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