bluedoor data·Job Postings API·bluedoor.sh ↗

Home › Companies › Aalyria Technologies, Inc. › Lead RTL/FPGA Design Engineer

Lead RTL/FPGA Design Engineer

Aalyria Technologies, Inc. · Remote (United States), United States · Remote · Active · $170,000–$195,000 / year · Rippling ATS

Job facts

FieldValue
CompanyAalyria Technologies, Inc.
TitleLead RTL/FPGA Design Engineer
Normalized title-
Department / teamSpace
LocationUnited States
Work modelRemote / Remote
Employment typeFull Time
Salary$170,000–$195,000 / year
Statusactive
ATS providerRippling ATS
Posted / first seen2026-04-23 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Aalyria Technologies, Inc..Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Rippling ATS.Open
Provider filtered searchThe same provider as a filtered job collection.Open
Department jobsActive postings in Space.Open
Work model jobsActive Remote postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyAalyria Technologies, Inc.
Sourceb96cc765-c456-47ad-ba49-ce552822da8d
ATS providerRippling ATS

Description

company About Aalyria: Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any hardware across land, sea, air, and space. role Role Overview: As the Lead RTL/FPGA Design Engineer on our Aalyria Space team, you will own the end to end the development of a high-performance coherent modem targeting free space optical (FSO) communications. In this role, you'll own the RTL development of that modem from architecture through silicon bring-up. That means translating complex DSP algorithms, equalization, carrier recovery, timing recovery, into clean, synthesizable RTL, integrating high-throughput FEC engines, and ensuring the full design meets the demanding power, performance, and area targets required for a fielded aerospace system. You'll work directly alongside DSP algorithm developers and system architects, serving as the bridge between mathematical models and working hardware. This is a remote position that will include occasional travel to our Mountain View office location. Key Responsibilities: Deliver end-to-end FPGA Modem Solution based on VHDL or System Verilog. Lead the micro-architecture and RTL development for key digital signal processing (DSP) blocks in the coherent modem, including equalization, carrier recovery, and timing recovery. Oversee the integration of Forward Error Correction (FEC) engines and high-speed interfaces into the overall modem architecture. Collaborate with system architects and DSP algorithm developers to translate DSP algorithm specification/ models into robust RTL designs. Design fixed-point arithmetic RTL implementation of complex DSP blocks. Ensure the design is compliant with relevant industry or company standards and specifications. Apply low power design techniques and perform power, performance, and area (PPA) analysis. Verify intended functionality using thorough test benches, and via vector matching with system models. Support functional verification, debug, and static timing closure. Collaborate closely with firmware/software engineers to define hardware/software partitioning, define registers and interfaces, and support system-level integration and debug. Support silicon bring-up and bench testing. Required Qualifications: Active Security Clearance, or the eligibility to obtain one. Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field. 5+ years of hands-on experience in RTL design for high-speed digital communications or related systems. Proficiency in logic design concepts and high-quality RTL coding using VDHL/SystemVerilog. Proven experience in micro-architecture definition and delivering detailed design specifications. Demonstrated ability to ensure RTL designs are compliant with relevant industry or company standards and specifications. Preferred Qualifications: Prior experience delivering an end-to-end FPGA communication system solution (from architecture to successful hardware validation). Deep expertise in implementing complex DSP functions in RTL, such as adaptive equalization, carrier recovery, and timing recovery. Proven experience in the integration of high-throughput FEC engines (e.g., LDPC, Reed-Solomon) into a high-speed data path. Ability to convert system models (e.g., Matlab or C++) into robust fixed-point RTL implementations, including successful vector matching and verification. Familiarity with high-speed ASIC/FPGA synthesis, place and route (P&R), and static timing analysis (STA) flows. Experience in designing for low power and high-speed multi-gigabit/sec interfaces. Exposure to the MAC layer (Media Access Control) or digital interface layers adjacent to the PHY. Experience with Python, Perl, TCL and/or other scripting languages. Experience with SoC (System-on-Chip) architectures, including design integration and verification involving embedded processors (e.g., ARM). Familiarity with defining and implementing hardware/software interface protocols for configuration and control. Prior experience with coherent modem architectures or free space optical (FSO) communications systems is highly desired. What We Offer: Innovative Environment: Work at a cutting-edge company shaping the future of aerospace communications. Impactful Work: Directly contribute to critical national security programs and initiatives. Growth Opportunities: Expand your career with opportunities for professional development and advancement. Inclusive Culture: Be part of a collaborative, supportive, and inclusive workplace where your contributions matter. Flexibility: Flexible working arrangements including hybrid remote/in-office schedules. Compensation and Equity: Competitive salary, comprehensive benefits (401(k), dental, vision, health, life insurance), paid time off, and equity options. ITAR/EAR Requirements: This position involves access to export-controlled information. To comply with U.S. government export regulations, applicants must meet one of the following criteria: (A) Qualify as a U.S. person, which includes: U.S. citizen or national U.S. lawful permanent resident (green card holder) Refugee under 8 U.S.C. 1157 Asylee under 8 U.S.C. 1158 (B) Be eligible to access export-controlled information without requiring an export authorization. (C) Be eligible and reasonably likely to obtain the necessary export authorization from the appropriate U.S. government agency. The company reserves the right to decline pursuing an export licensing process for legitimate business-related reasons. Equal Opportunity Employer Statement: Aalyria is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We do not discriminate based on race, color, religion, sex (including pregnancy, gender identity, and sexual orientation), national origin, age, disability status, genetic information, protected veteran status, or any other characteristic protected by law. Qualified applicants from all backgrounds are encouraged to apply.

Full job record

Job ID963e446d371bd85cb87ec3264a50333dc99b7c3e
Org ID2b17852d-2cdb-446b-b0cb-81dbe914b2d8
Source IDb96cc765-c456-47ad-ba49-ce552822da8d
Board IDb96cc765-c456-47ad-ba49-ce552822da8d
Providerrippling
Provider Job Key3197562c-262b-401d-85c6-08e683936531
TitleLead RTL/FPGA Design Engineer
Normalized Title—
Statusactive
Activeyes
Location TextRemote (United States), United States
DepartmentSpace
Team—
Employment Typefull_time
Workplace Typeremote
Remote Policyremote
CountryUnited States
Region—
City—
Salary RawUSD 170000-195000 YEAR
Salary Min170,000
Salary Max195,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://ats.rippling.com/aalyria-careers/jobs/3197562c-262b-401d-85c6-08e683936531
Apply URLhttps://ats.rippling.com/aalyria-careers/jobs/3197562c-262b-401d-85c6-08e683936531
First Seen At2026-05-29 07:12:01Z
Last Seen At2026-06-06 08:44:31Z
Last Checked At2026-06-06 08:44:31Z
Last Changed At2026-06-06 08:44:31Z
Inactive At—
Source Posted At2026-04-23 18:23:04Z
Source Updated At—
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=rippling/board=aalyria-careers/date=2026-06-06/2026-06-06T08-44-29-914Z-8241b1ec74c940463e82502823039eb2dca3f1566be677862b32096d71639ff9.json
Event Fields
{
  "content_hash": "163c0338e856f5bbcb83fa12af42c5a6118bed94fcf871b51b392c2f066e21e9",
  "source_hash": "6d1a395f1b95f39b24c52bdd8442fc538bc2d5cf9e4a9047aa5cfeabefa18a91",
  "last_changed_at": "2026-06-06T08:44:31.027Z",
  "active_status": "active"
}
Parsed Structured
{
  "language": "en-us",
  "location": {
    "raw": "Remote (United States), United States",
    "city": null,
    "region": null,
    "country": "United States",
    "is_remote": true,
    "confidence": 0.98,
    "workplace_type": "remote"
  },
  "salary_max": 195000,
  "salary_min": 170000,
  "inferred_at": "2026-06-06T08:44:31.011Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en-us",
    "location": {
      "raw": "Remote (United States), United States",
      "city": null,
      "region": null,
      "country": "United States",
      "is_remote": true,
      "confidence": 0.98,
      "workplace_type": "remote"
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": "remote",
  "salary_period": "year",
  "workplace_type": "remote",
  "salary_currency": "USD"
}
Extensions
{}
Native Structured
{
  "list_job": {
    "id": "3197562c-262b-401d-85c6-08e683936531",
    "url": "https://ats.rippling.com/aalyria-careers/jobs/3197562c-262b-401d-85c6-08e683936531",
    "name": "Lead RTL/FPGA Design Engineer",
    "language": "en-US",
    "locations": [
      {
        "city": "",
        "name": "Remote (United States)",
        "state": "",
        "country": "United States",
        "stateCode": null,
        "countryCode": "US",
        "workplaceType": "REMOTE"
      }
    ],
    "department": {
      "name": "Space"
    }
  },
  "detail_job": {
    "url": "https://ats.rippling.com/aalyria-careers/jobs/3197562c-262b-401d-85c6-08e683936531",
    "name": "Lead RTL/FPGA Design Engineer",
    "uuid": "3197562c-262b-401d-85c6-08e683936531",
    "board": {
      "logo": {
        "url": "https://prod-images.rippling.com/dc8161eb5748e0464ccf66bb0523def4a5fbeaf0.png?Expires=1780821870&Signature=TkGBagqYSbZq6Ep5glLf8kLz86G1O-IMDh36xyioCGYXTrBCKisjeV9bR6ZJ8CX4dH7kExSgj5BKWyO2ApfnvoH9~66fgFVVT1hIKLVLUrDYWUe~kfKDKJXBJv38kM3cHTkygAvrl01h9s4GkrpVnR7EKuCPT0AK18ZkkCM5QwwdbKnmjFQOPWg37Tl83MmsI1TakIvuYgCYK2u8V9wHA7HHHBvQ7nN9Wgc5J6njlV7HldJ6t14kz1yOBpSA7Lk2p75nax~qUDQ4YAZOV3DVijqYTBcuA6L-nwXNS9qk63BaRKp6TSkV~-GENQOP9euaoO8oYbcsQRHx3h2awmE7Bg__&Key-Pair-Id=K2Y26R2ZPP26PH",
        "name": "AALYRIA_PrimaryWordmark_1Color_HighRes (1).png",
        "type": "image/png"
      },
      "slug": "aalyria-careers",
      "title": "Careers at Aalyria",
      "banner": {
        "url": null,
        "name": "",
        "type": ""
      },
      "boardURL": "https://ats.rippling.com/aalyria-careers/jobs",
      "fontType": "ARIAL_SANS_SERIF",
      "subtitle": "Explore exciting career opportunities at Aalyria and join our mission to build cutting-edge technology with a team that values innovation, impact, and growth.",
      "boardType": "RIPPLING",
      "linkColor": null,
      "buttonColor": null,
      "legalNotice": "<meta name=\"rteConfig\" content=\"{&quot;version&quot;:&quot;0.152.0&quot;}\"><p style=\"font-style:normal;font-weight:400;font-size:11pt;line-height:1.38;font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;margin-right:0px;padding:0px;margin-top:0px;margin-bottom:0px;\"><br></p>",
      "buttonTextColor": null,
      "noOpeningsMessage": null,
      "groupJobsByLocation": false,
      "showBoardLogoOnJobPost": false,
      "showCompanyInfoUnderJobPost": false
    },
    "createdOn": "2026-04-23T11:23:04.390000-07:00",
    "department": {
      "name": "Space",
      "base_department": "Space",
      "department_tree": [
        "Space"
      ]
    },
    "companyName": "Aalyria Technologies, Inc.",
    "description": {
      "role": "<meta><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Role Overview:</strong></b></h2><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">As the Lead RTL/FPGA Design Engineer on our Aalyria Space team, you will own the end to end the development of a high-performance coherent modem targeting free space optical (FSO) communications. In this role, you'll own the  RTL development of that modem from architecture through silicon bring-up. That means translating complex DSP algorithms, equalization, carrier recovery, timing recovery, into clean, synthesizable RTL, integrating high-throughput FEC engines, and ensuring the full design meets the demanding power, performance, and area targets required for a fielded aerospace system. You'll work directly alongside DSP algorithm developers and system architects, serving as the bridge between mathematical models and working hardware.  </span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">This is a remote position that will include occasional travel to our Mountain View office location.</span></p><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Key Responsibilities:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Deliver end-to-end FPGA Modem Solution based on VHDL or System Verilog.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Lead the micro-architecture and RTL development for key digital signal processing (DSP) blocks in the coherent modem, including equalization, carrier recovery, and timing recovery.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Oversee the integration of Forward Error Correction (FEC) engines and high-speed interfaces into the overall modem architecture.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Collaborate with system architects and DSP algorithm developers to translate DSP algorithm specification/ models into robust RTL designs.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Design fixed-point arithmetic RTL implementation of complex DSP blocks.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Ensure the design is compliant with relevant industry or company standards and specifications.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Apply low power design techniques and perform power, performance, and area (PPA) analysis.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Verify intended functionality using thorough test benches, and via vector matching with system models.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Support functional verification, debug, and static timing closure.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Collaborate closely with firmware/software engineers to define hardware/software partitioning, define registers and interfaces, and support system-level integration and debug.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Support silicon bring-up and bench testing.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Required Qualifications:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Active Security Clearance, or the eligibility to obtain one.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">5+ years of hands-on experience in RTL design for high-speed digital communications or related systems.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Proficiency in logic design concepts and high-quality RTL coding using VDHL/SystemVerilog.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Proven experience in micro-architecture definition and delivering detailed design specifications.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Demonstrated ability to ensure RTL designs are compliant with relevant industry or company standards and specifications.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Preferred Qualifications:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Prior experience delivering an end-to-end FPGA communication system solution (from architecture to successful hardware validation).</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Deep expertise in implementing complex DSP functions in RTL, such as adaptive equalization, carrier recovery, and timing recovery.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Proven experience in the integration of high-throughput FEC engines (e.g., LDPC, Reed-Solomon) into a high-speed data path.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Ability to convert system models (e.g., Matlab or C++) into robust fixed-point RTL implementations, including successful vector matching and verification.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Familiarity with high-speed ASIC/FPGA synthesis, place and route (P&amp;R), and static timing analysis (STA) flows.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience in designing for low power and high-speed multi-gigabit/sec interfaces.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Exposure to the MAC layer (Media Access Control) or digital interface layers adjacent to the PHY.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with Python, Perl, TCL and/or other scripting languages.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with SoC (System-on-Chip) architectures, including design integration and verification involving embedded processors (e.g., ARM).</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Familiarity with defining and implementing hardware/software interface protocols for configuration and control.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Prior experience with coherent modem architectures or free space optical (FSO) communications systems is highly desired.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">What We Offer:</strong></b></h2><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Innovative Environment: </strong></b><span style=\"white-space:pre-wrap;\">Work at a cutting-edge company shaping the future of aerospace communications.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Impactful Work:</strong></b><span style=\"white-space:pre-wrap;\"> Directly contribute to critical national security programs and initiatives.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Growth Opportunities: </strong></b><span style=\"white-space:pre-wrap;\">Expand your career with opportunities for professional development and advancement.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Inclusive Culture:</strong></b><span style=\"white-space:pre-wrap;\"> Be part of a collaborative, supportive, and inclusive workplace where your contributions matter.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Flexibility: </strong></b><span style=\"white-space:pre-wrap;\">Flexible working arrangements including hybrid remote/in-office schedules.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"white-space:pre-wrap;\">Compensation and Equity:</strong></b><span style=\"white-space:pre-wrap;\"> Competitive salary, comprehensive benefits (401(k), dental, vision, health, life insurance), paid time off, and equity options.</span></li></ul><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">ITAR/EAR Requirements:</strong></b></h2><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">This position involves access to export-controlled information. To comply with U.S. government export regulations, applicants must meet one of the following criteria:</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">(A) Qualify as a U.S. person, which includes:</span></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">U.S. citizen or national</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">U.S. lawful permanent resident (green card holder)</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Refugee under 8 U.S.C. 1157</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Asylee under 8 U.S.C. 1158</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">(B) Be eligible to access export-controlled information without requiring an export authorization.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">(C) Be eligible and reasonably likely to obtain the necessary export authorization from the appropriate U.S. government agency.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">The company reserves the right to decline pursuing an export licensing process for legitimate business-related reasons.</span></p><h2 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:15pt;font-weight:600;letter-spacing:0.5px;margin-top:18px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Equal Opportunity Employer Statement:</strong></b></h2><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">Aalyria is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We do not discriminate based on race, color, religion, sex (including pregnancy, gender identity, and sexual orientation), national origin, age, disability status, genetic information, protected veteran status, or any other characteristic protected by law. Qualified applicants from all backgrounds are encouraged to apply.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p>",
      "company": "<meta><h1 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:1px;margin-top:24px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">About Aalyria:</strong></b></h1><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any hardware across land, sea, air, and space.</span></p>"
    },
    "workLocations": [
      "Remote (United States)"
    ],
    "employmentType": {
      "id": "Salaried, full-time",
      "label": "SALARIED_FT"
    },
    "payRangeDetails": [
      {
        "currency": "USD",
        "isRemote": true,
        "location": "Remote (United States)",
        "rangeEnd": 195000,
        "frequency": "YEAR",
        "rangeStart": 170000
      },
      {
        "currency": "USD",
        "isRemote": true,
        "location": "Remote (San Francisco Bay Area, California)",
        "rangeEnd": 215000,
        "frequency": "YEAR",
        "rangeStart": 185000
      }
    ],
    "activeJobApplication": {
      "basicQuestions": [
        {
          "oid": "first_name",
          "title": "First name",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "last_name",
          "title": "Last name",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "email",
          "title": "Email",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "pronouns",
          "title": "Pronouns",
          "required": false,
          "fieldType": "PRONOUN"
        },
        {
          "oid": "current_company",
          "title": "Current company",
          "required": false,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "phone_number",
          "title": "Phone number",
          "required": true,
          "fieldType": "PHONE_NUMBER"
        },
        {
          "oid": "location",
          "title": "Location (city only)",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "linkedin_link",
          "title": "LinkedIn link",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "website_link",
          "title": "Website link",
          "required": false,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "resume",
          "title": "Resume",
          "required": true,
          "fieldType": "FILE"
        },
        {
          "oid": "cover_letter",
          "title": "Cover letter",
          "required": false,
          "fieldType": "FILE"
        }
      ],
      "customQuestions": {
        "fields": [
          {
            "oid": "first_name",
            "title": "First name",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "last_name",
            "title": "Last name",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "email",
            "title": "Email",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "pronouns",
            "title": "Pronouns",
            "required": false,
            "fieldData": {},
            "fieldType": "PRONOUN"
          },
          {
            "oid": "current_company",
            "title": "Current company",
            "required": false,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "phone_number",
            "title": "Phone number",
            "required": true,
            "fieldData": {},
            "fieldType": "PHONE_NUMBER"
          },
          {
            "oid": "location",
            "title": "Location (city only)",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "linkedin_link",
            "title": "LinkedIn link",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "website_link",
            "title": "Website link",
            "required": false,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "resume",
            "title": "Resume",
            "required": true,
            "fieldData": {},
            "fieldType": "FILE"
          },
          {
            "oid": "cover_letter",
            "title": "Cover letter",
            "required": false,
            "fieldData": {},
            "fieldType": "FILE"
          }
        ]
      },
      "additionalQuestions": [
        {
          "id": "69ebfbdadc81b668d099bbf1",
          "form": {
            "sections": [],
            "questions": [
              {
                "tags": [],
                "title": "Are you legally authorized to work in the United States?",
                "canEdit": false,
                "dataType": "enum",
                "isPrivate": false,
                "uniqueKey": "40ab54c6-0f77-4f80-9bf4-b5e70daac124",
                "intChoices": [],
                "isRequired": true,
                "strChoices": [
                  "Yes",
                  "No"
                ],
                "questionType": "SINGLE_SELECT_RADIO",
                "allowComments": false,
                "isOtherEnabled": false,
                "isMultiSelectEnabled": false
              },
              {
                "tags": [],
                "title": "This position may involve access to technology or technical data subject to U.S. export control laws and regulations, including EAR and ITAR. Are you a U.S. Person as defined under these regulations (U.S. citizen, U.S. national, lawful permanent resident, or protected individual under 8 U.S.C. 1324b(a)(3))?",
                "canEdit": false,
                "dataType": "enum",
                "isPrivate": false,
                "uniqueKey": "d1a08496-c832-4fa1-9d71-6a460da7739b",
                "intChoices": [],
                "isRequired": true,
                "strChoices": [
                  "Yes",
                  "No"
                ],
                "questionType": "SINGLE_SELECT_RADIO",
                "allowComments": false,
                "isOtherEnabled": false,
                "isMultiSelectEnabled": false
              },
              {
                "tags": [],
                "title": "Do you currently, or will you in the future, require sponsorship for employment authorization (e.g., H-1B or other work visas)?",
                "canEdit": false,
                "dataType": "enum",
                "isPrivate": false,
                "uniqueKey": "b91339c1-d009-45b8-9fc9-6202c30216a0",
                "intChoices": [],
                "isRequired": true,
                "strChoices": [
                  "Yes",
                  "No"
                ],
                "questionType": "SINGLE_SELECT_RADIO",
                "allowComments": false,
                "isOtherEnabled": false,
                "isMultiSelectEnabled": false
              },
              {
                "tags": [],
                "title": "Do you currently possess an active security clearance (Confidential / Secret / Top Secret / TS-SCI) with the US Government? If yes, please list what level.",
                "canEdit": false,
                "dataType": "enum",
                "isPrivate": false,
                "uniqueKey": "7b156eae-d455-4355-8ee7-156cbd2a8d8f",
                "intChoices": [],
                "isRequired": true,
                "strChoices": [
                  "Yes",
                  "No"
                ],
                "questionType": "SINGLE_SELECT_RADIO",
                "allowComments": true,
                "isOtherEnabled": false,
                "isMultiSelectEnabled": false
              }
            ],
            "skipLogic": [],
            "deletedSections": [],
            "deletedQuestions": [
              {
                "tags": [],
                "title": "Are you legally authorized to work in the United States?",
                "canEdit": false,
                "dataType": "enum",
                "isPrivate": false,
                "uniqueKey": "bd7d8392-7118-4594-a9eb-ac01ddd1fd34",
                "intChoices": [],
                "isRequired": false,
                "strChoices": [
                  "Yes",
                  "No"
                ],
                "description": "",
                "questionType": "SINGLE_SELECT_RADIO",
                "allowComments": false,
                "isOtherEnabled": false,
                "isMultiSelectEnabled": false
              }
            ]
          },
          "name": "[REQUIRED] US Applicant Questionnaire"
        }
      ]
    },
    "hasAIEvaluationsEnabled": false,
    "eeocQuestionnaireEnabled": true,
    "applicationConfirmationTemplate": "67e3004fb4c2ca5efaf18f61",
    "eeocQuestionnaireEnabledForJobPost": true
  },
  "detail_meta": {
    "url": "https://ats.rippling.com/api/v2/board/aalyria-careers/jobs/3197562c-262b-401d-85c6-08e683936531",
    "http_status": 200,
    "content_type": "application/json",
    "response_bytes": 25214
  },
  "detail_errors": []
}
Get this page with API

Rendered from the bluedoor Job Postings API. Reproduce it:

GET https://api.bluedoor.sh/job-postings/v1/jobs/963e446d371bd85cb87ec3264a50333dc99b7c3e?include=descriptionJSON
GET https://api.bluedoor.sh/job-postings/v1/orgs/2b17852d-2cdb-446b-b0cb-81dbe914b2d8JSON
GET https://api.bluedoor.sh/job-postings/v1/sources/b96cc765-c456-47ad-ba49-ce552822da8dJSON
GET https://api.bluedoor.sh/job-postings/v1/jobs/963e446d371bd85cb87ec3264a50333dc99b7c3e/eventsJSON

Docs · Get an API key