FPGA Engineer

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    "description": "<p><span style=\"font-family: Inter, sans-serif; font-weight: bold\">Responsibilities</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Algorithm implementation: Translate complex probabilistic algorithms from high-level </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">models, such as pseudocode/Python/C++/MATLAB, into highly pipelined, resource-efficient </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">FPGA RTL.</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">RTL design from scratch: Design and implement custom digital logic using VHDL where </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">off-the-shelf vendor IPs are insufficient, bottlenecked, or introduce latency.</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">High-speed I/O integration: architect data acquisition pipelines interfacing with the </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">analogue front end via ultra-fast ADCs and high-speed transceivers, as well as interfacing to </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">high-throughput computer host architectures via PCIe and high-speed Ethernet.</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">System architecture: Work closely with hardware and software engineers, the research </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">team, and ASIC architects to develop the high-level system architecture.</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Verification &amp; bring-up: Develop rigorous testbenches and simulations to ensure </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">compliance with functional and timing requirements. Participate in lab bring-up and </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">debugging of physical hardware. </span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Optimisation: Use advanced debugging tools and techniques to analyse and optimise </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">performance, timing closure, power consumption, and resource utilisation across multiple </span><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">clock domains.</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-weight: bold\">Requirements</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Degree in Electrical Engineering, Computer Engineering, or a related field.</span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">5+ years of hands-on experience in FPGA digital design, including designing and debugging </span><span style=\"font-family: Inter, sans-serif\">resource-intensive high-speed digital systems.</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Expertise in HDL: Strong proficiency in HDL coding, and a proven track record of writing </span><span style=\"font-family: Inter, sans-serif\">custom RTL from scratch.</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">PS/Embedded development knowledge: Practical understanding of processor-side </span><span style=\"font-family: Inter, sans-serif\">development for FPGA SoC platforms, particularly Zynq or similar PS/PL architectures. </span><span style=\"font-family: Inter, sans-serif\">Being comfortable writing or reviewing bare-metal C/C++ to configure PL peripherals </span><span style=\"font-family: Inter, sans-serif\">through AXI registers, moving data between PS and PL.</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Math to hardware: Proven ability to translate complex mathematical models into </span><span style=\"font-family: Inter, sans-serif\">hardware accelerators, including bit-accurate system modelling and fixed-point arithmetic.</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Digital design fundamentals: Solid understanding of advanced digital design concepts, </span><span style=\"font-family: Inter, sans-serif\">including timing closure for highly utilised designs and clock domain crossing (CDC).</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Toolchains: Deep experience with design and verification tools such as Xilinx Vivado, Vitis, </span><span style=\"font-family: Inter, sans-serif\">and TCL scripting.</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Lab/debug skills: Familiarity with hardware debugging tools, such as JTAG debuggers, </span><span style=\"font-family: Inter, sans-serif\">oscilloscopes, spectrum analysers, signal generators, and logic analysers, and lab bring-up </span><span style=\"font-family: Inter, sans-serif\">of custom boards.</span></span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-weight: bold\">What makes you stand out</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Synchronised FPGA interconnect network within a scalable cluster approach.</span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Demonstrated experience with implementing stochastic problems, optimisation algorithms, </span><span style=\"font-family: Inter, sans-serif\">neural network, or artificial intelligence / machine learning algorithms into hardware.</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Direct experience with the ASIC design flow: act as the critical bridge towards custom </span><span style=\"font-family: Inter, sans-serif\">silicon by prototyping, emulating, and validating our probabilistic computing architectures </span><span style=\"font-family: Inter, sans-serif\">on FPGA platforms prior to ASIC tape-out.</span></span></li>\n<li><span style=\"font-size: 12pt\"><span style=\"font-family: Inter, sans-serif\">Experience designing highly optimised, low-latency computing architectures, such as high-</span><span style=\"font-family: Inter, sans-serif\">frequency trading, custom digital signal processing, or high-performance computing</span></span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-size: 12pt\"><span style=\"font-weight: bold\">Why join us?</span></span></p>\n<ul>\n<li><span style=\"font-size: 12pt\">It's an exciting time to work in probabilistic computing and you’ll be defining the libraries for an entirely new class of computer.</span></li>\n<li><span style=\"font-size: 12pt\">We maintain strong ties to the University of Oxford, offering a vibrant intellectual environment and access to world-leading experts.</span></li>\n<li><span style=\"font-size: 12pt\">Our technology targets critical real-world sectors, including logistics, drug discovery, and climate modeling.</span></li>\n<li><span style=\"font-size: 12pt\">We are a diverse team of passionate thinkers meeting builders. We value curiosity, transparency and a good sense of humour.</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-size: 12pt\"><span style=\"font-weight: bold\">Quantum Dice is an equal opportunity employer.</span> We celebrate diversity and are committed to creating an inclusive environment for all employees.</span></p>",
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