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Lead QPU Design Engineer

Quantummotion · London, UK · Hybrid · Active · Personio

Job facts

Field	Value
Company	Quantummotion
Title	Lead QPU Design Engineer
Normalized title	-
Department / team	QPU Design / Permanent
Location	London, UK
Work model	Hybrid / Hybrid
Employment type	Full Time
Salary	-
Status	active
ATS provider	Personio
Posted / first seen	2026-02-18 / 2026-05-30
Changed / last seen	2026-05-30 / 2026-06-06

Related slices

Page	What it contains	Open
Company jobs	Active postings from Quantummotion.	Open
Company breakdowns	Role, location, ATS, and work model facets for this company.	Open
ATS provider jobs	Active postings observed through Personio.	Open
Provider filtered search	The same provider as a filtered job collection.	Open
Department jobs	Active postings in QPU Design.	Open
Work model jobs	Active Hybrid postings.	Open
Lifecycle events	Open, update, close, and reopen events for this posting.	Open
Original posting	Canonical source or apply URL captured from the ATS.	Open

Linked records

Company	Quantummotion
Source	89819de8-f7af-4b79-a7ff-f42b278011b3
ATS provider	Personio

Description

About The Role and Team Quantum Motion is a fast-growing quantum computing scale-up based in London. We are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence and more. Our Team Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times , and our technology breakthroughs have been featured in The Telegraph , BBC and the New Statesman . Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors, and we have recently closed our Series C funding of $160 million. We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology. Our team of 100+ is based in Oxford and London, with a centre of mass in our Islington lab. Functions of the Role We are hiring a Lead QPU Design Engineer to lead end-to-end design execution for silicon spin qubit quantum processor units (QPUs) and test vehicles, from concept through tapeout. This is a unique opportunity to work at the boundary between quantum physics and semiconductor engineering, exploring new device concepts while building industry-standard infrastructure for manufacturability. This is a hybrid hands-on execution and team leadership role. You will personally implement critical work (layout or simulation, depending on your background) while defining standards, running reviews, and managing a complementary team. We are open to candidates whose primary expertise is in layout or simulation. You must have working fluency in the other, enough to review critically and integrate effectively. Functions of the Role Translate qubit architecture requirements into manufacturable physical designs: gate layouts, bias networks, and multi-qubit interconnects. Define connectivity/schematic capture and generate netlists for circuit simulation and LVS verification. Own tapeouts, including readiness reviews, verification, risk management. Execute critical design work in your domain (layout or simulation); review and integrate the other. Collaborate with experimentalists and the device modelling team to refine designs and device models based on fabrication constraints and simulation results. Define design workflows, standards, toolchains, and guide PDK and DFT development. Lead and mentor the QPU Design team. Experience - Essentials PhD or equivalent experience in EE, physics, or a related field. 8+ years in experimental hardware within research-adjacent environments industry environments. Led hardware from concept through tapeout with personal accountability. Deep expertise in one domain with fluency in the either domain: Layout-first : custom physical design of block- and chip-level layouts using Cadence Virtuoso or similar. Hands-on DRC/LVS/extraction. Personally owned tapeouts. Worked with sim teams, ran basic TCAD/EM, debugged layout via sim. Simulation-first : EM/electrostatic/circuit modeling using relevant tools such as Ansys (HFSS/Q3D), Keysight ADS, Cadence Spectre, Synopsys Sentaurus, or equivalent. Validated models against measured data. Iterated on layouts, understand best practices and DRC constraints, constructively critiqued layout decisions. Understanding of semiconductor device physics. Built processes, mentored engineers, and integrated across physics/sim/layout. Experience - Desirable Silicon spin qubit, quantum dot, or superconducting qubit experience. Understanding of CMOS process integration, 3D integration and/or advanced packaging. Microwave circuit design experience. Scripting (Python, SKILL, Tcl) for design automation. Experience correlating simulations with low-temperature measurements. Benefits Be part of a creative, world-leading team Competitive salary and share options scheme Contributory pension scheme Group private medical insurance scheme Life Assurance Cycle-to-work Scheme Central London location EEO Statement Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010.

Full job record

Job ID	9218a647e1b055846406fdb8b1aa48b400e41cf9
Org ID	d9ca52c0-6658-41d7-83d0-d6c3fee3fbe0
Source ID	89819de8-f7af-4b79-a7ff-f42b278011b3
Board ID	89819de8-f7af-4b79-a7ff-f42b278011b3
Provider	personio
Provider Job Key	2535320
Title	Lead QPU Design Engineer
Normalized Title	—
Status	active
Active	yes
Location Text	London, UK
Department	QPU Design
Team	Permanent
Employment Type	full_time
Workplace Type	hybrid
Remote Policy	hybrid
Country	—
Region	—
City	—
Salary Raw	—
Salary Min	—
Salary Max	—
Salary Currency	—
Salary Period	—
Source URL	https://quantummotion.jobs.personio.com/job/2535320?language=en
Apply URL	https://quantummotion.jobs.personio.com/job/2535320?language=en
First Seen At	2026-05-30 05:56:56Z
Last Seen At	2026-06-06 07:59:02Z
Last Checked At	2026-06-06 07:59:02Z
Last Changed At	2026-05-30 05:56:56Z
Inactive At	—
Source Posted At	2026-02-18 16:01:53Z
Source Updated At	—
Raw Payload Uri	s3://job-postings-prod-raw-590183727216/raw/provider=personio/board=quantummotion.com/date=2026-06-06/2026-06-06T07-59-01-508Z-60a79605d5ff79f06a928c70ac207dfe6f6fb66ba34767b79ead76890f631503.json

Event Fields

{
  "content_hash": "a5b5ece7fbe438e4abbfc37378da21888ceda1746a9c8c92362e653e252b75f7",
  "source_hash": "b74c66325a2692e9fe68fad483ed1adf3c49b93bd3ee3c9fb45c421acb513ab0",
  "last_changed_at": "2026-05-30T05:56:56.302Z",
  "active_status": "active"
}

Parsed Structured

{
  "language": "en",
  "location": {
    "raw": "London, UK",
    "city": null,
    "region": null,
    "country": null,
    "is_remote": false,
    "confidence": 0.8
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-06T07:59:02.287Z",
  "launch_scope": {
    "reason": "personio_production_catalog",
    "included": true,
    "location": {
      "raw": "London, UK",
      "city": null,
      "region": null,
      "country": null,
      "is_remote": false,
      "confidence": 0.8
    },
    "countries": []
  },
  "remote_policy": "hybrid",
  "salary_period": null,
  "workplace_type": "hybrid",
  "salary_currency": null
}

Extensions

{}

Native Structured

{
  "id": "2535320",
  "name": "Lead QPU Design Engineer",
  "office": "London, UK",
  "keywords": [],
  "schedule": "full-time",
  "createdAt": "2026-02-18T16:01:53+00:00",
  "seniority": "experienced",
  "department": "QPU Design",
  "occupation": "general_and_other_r_and_d_and_science",
  "subcompany": "QUANTUM MOTION TECHNOLOGIES LIMITED",
  "employmentType": "permanent",
  "jobDescriptions": [
    {
      "name": "About The Role and Team",
      "value": "<span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Quantum Motion is a fast-growing quantum computing scale-up based in London. We are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence and more. </span>"
    },
    {
      "name": "Our Team",
      "value": "<p>Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” <a style=\"text-decoration:none;\" href=\"https://www.eetimes.com/product/silicon-100-startups-worth-watching-in-2021/\">in the EE Times</a>, and our technology breakthroughs have been featured in <a style=\"text-decoration:none;\" href=\"https://www.telegraph.co.uk/technology/2021/04/01/quantum-computing-breakthrough-speed-roll-decades/\">The Telegraph</a>, <a style=\"text-decoration:none;\" href=\"https://www.bbc.co.uk/news/technology-56614278\">BBC</a> and the <a style=\"text-decoration:none;\" href=\"https://www.newstatesman.com/international/2021/04/risks-creating-arms-race-inside-europes-battle-over-future-quantum-computing\">New Statesman</a>. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. <span style=\"font-size:10.5pt;font-family:Arial, sans-serif;color:#424242;background-color:#ffffff;font-weight:400;font-style:normal;text-decoration:none;\"><span style=\"font-size:10.5pt;font-family:Arial, sans-serif;color:#424242;background-color:#ffffff;font-weight:400;font-style:normal;text-decoration:none;\">We’re backed by a team of top-tier investors, and we have recently closed our </span><span style=\"font-size:10.5pt;font-family:Arial, sans-serif;color:#424242;background-color:#ffffff;font-weight:400;font-style:normal;text-decoration:none;\"><a target=\"_blank\" href=\"https://quantummotion.com/series-c-funding/\" rel=\"noreferrer noopener\">Series C funding of $160 million.</a></span></span></p><p>We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology.</p><br><p>Our team of 100+ is based in Oxford and London, with a centre of mass in our Islington lab.</p>"
    },
    {
      "name": "Functions of the Role",
      "value": "<p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">We are hiring a Lead QPU Design Engineer to lead end-to-end design execution for silicon spin qubit quantum processor units (QPUs) and test vehicles, from concept through tapeout. This is a unique opportunity to work at the boundary between quantum physics and semiconductor engineering, exploring new device concepts while building industry-standard infrastructure for manufacturability.</span></p><br><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">This is a hybrid hands-on execution and team leadership role. You will personally implement critical work (layout or simulation, depending on your background) while defining standards, running reviews, and managing a complementary team.</span></p><br><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">We are open to candidates whose primary expertise is in layout or simulation. You must have working fluency in the other, enough to review critically and integrate effectively. </span></p><br><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:700;font-style:normal;text-decoration:none;\">Functions of the Role </span></p><ul style=\"margin-top:0;margin-bottom:0;\"><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:700;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Translate qubit architecture requirements into manufacturable physical designs: gate layouts, bias networks, and multi-qubit interconnects. </span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Define connectivity/schematic capture and generate netlists for circuit simulation and LVS verification.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:700;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Own tapeouts, including readiness reviews, verification, risk management.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Execute critical design work in your domain (layout or simulation); review and integrate the other.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Collaborate with experimentalists and the device modelling team to refine designs and device models based on fabrication constraints and simulation results.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Define design workflows, standards, toolchains, and guide PDK and DFT development.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Lead and mentor the QPU Design team.</span></p></li></ul>"
    },
    {
      "name": "Experience - Essentials",
      "value": "<ul style=\"margin-top:0;margin-bottom:0;\"><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">PhD or equivalent experience in EE, physics, or a related field.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">8+ years in experimental hardware within research-adjacent environments industry environments.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Led hardware from concept through tapeout with personal accountability.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Deep expertise in one domain with fluency in the either domain:</span></p><ul style=\"margin-top:0;margin-bottom:0;\"><li style=\"list-style-type:circle;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:700;font-style:normal;text-decoration:none;\">Layout-first</span><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">: custom physical design of block- and chip-level layouts using Cadence Virtuoso or similar.</span></p><ul style=\"margin-top:0;margin-bottom:0;\"><li style=\"list-style-type:square;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Hands-on DRC/LVS/extraction.</span></p></li><li style=\"list-style-type:square;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Personally owned tapeouts.</span></p></li><li style=\"list-style-type:square;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:700;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Worked with sim teams, ran basic TCAD/EM, debugged layout via sim.</span></p></li></ul></li><li style=\"list-style-type:circle;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:700;font-style:normal;text-decoration:none;\">Simulation-first</span><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">: EM/electrostatic/circuit modeling using relevant tools such as Ansys (HFSS/Q3D), Keysight ADS, Cadence Spectre, Synopsys Sentaurus, or equivalent.</span></p><ul style=\"margin-top:0;margin-bottom:0;\"><li style=\"list-style-type:square;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Validated models against measured data.</span></p></li><li style=\"list-style-type:square;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:700;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Iterated on layouts, understand best practices and DRC constraints, constructively critiqued layout decisions.</span></p></li></ul></li></ul></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Understanding of semiconductor device physics.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Built processes, mentored engineers, and integrated across physics/sim/layout.</span></p></li></ul>"
    },
    {
      "name": "Experience - Desirable",
      "value": "<ul style=\"margin-top:0;margin-bottom:0;\"><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Silicon spin qubit, quantum dot, or superconducting qubit experience.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Understanding of CMOS process integration, 3D integration and/or advanced packaging.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Microwave circuit design experience.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Scripting (Python, SKILL, Tcl) for design automation.</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Experience correlating simulations with low-temperature measurements.</span></p></li></ul>"
    },
    {
      "name": "Benefits",
      "value": "<ul style=\"margin-top:0;margin-bottom:0;\"><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Be part of a creative, world-leading team</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Competitive salary and share options scheme</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Contributory pension scheme</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Group private medical insurance scheme</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Life Assurance</span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Cycle-to-work Scheme </span></p></li><li style=\"list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\"><p style=\"line-height:1.3800000000000001;margin-top:0pt;margin-bottom:0pt;\"><span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Central London location</span></p></li></ul>"
    },
    {
      "name": "EEO Statement",
      "value": "<span style=\"font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;\">Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010.</span>"
    }
  ],
  "occupationCategory": "r_and_d_and_science",
  "recruitingCategory": "Permanent"
}

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