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Principal Engineer, CAD

555e77b2 029a 4357 8712 1dd910b41621 19000101 000001 · Santa Clara, CA, US, Santa Clara, CA · Active · $164,800–$226,600 / year · ADP Workforce Now Recruiting

Job facts

FieldValue
Company555e77b2 029a 4357 8712 1dd910b41621 19000101 000001
TitlePrincipal Engineer, CAD
Normalized title-
Department / team-
LocationSanta Clara, CA, United States
Work model-
Employment typeFull Time
Salary$164,800–$226,600 / year
Statusactive
ATS providerADP Workforce Now Recruiting
Posted / first seen2026-04-28 / 2026-05-31
Changed / last seen2026-06-20 / 2026-06-20

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Linked records

Company555e77b2 029a 4357 8712 1dd910b41621 19000101 000001
Sourcec2707813-bcf1-47e7-bd8f-33621286a357
ATS providerADP Workforce Now Recruiting

Description

About SiTime SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com . Job Summary The Principal Engineer, CAD will provide CAD Software support for Digital, Analog and Mixed-Signal designs, using Cadence, Synopsys, Siemens, Keysight & 3 rd party vendor tools. Responsibilities include user support for Behavioral, RTL and Analog Designs, Schematics, Analog Mixed-Signal Simulations, IC Physical Design layout, CAD tool customizations, Linux Support, implementation and testing of new software tools and deploy new CAD Tool flows. The Principal CAD Engineer will also interface with EDA Tool Vendors and have responsibilities for implementation and performance testing of new software releases, prior to deploying to IC Designers across multiple engineering sites. Responsibilities: Provide full lifecycle support for custom CAD flows, including tool development, installation, configuration, maintenance and upgrades across Cadence, Synopsys, Siemens and Keysight platforms Own PDK installation, validation, customization, maintenance and release management, ensuring alignment with foundry and keeping up to date versions always ready Support and maintain end-to-end tapeout flows, including coordinating and executing tapeout submissions to foundries, ensuring compliance with foundry requirements, schedules and quality standards Support Schematic Capture, Analog and Mixed-signal Simulation, Layout and Layout Verification software and workflows using established revision-controlled processes Support and maintain digital simulation, verification environments, digital place-and-route tools Develop and maintain CAD utilities, automation scripts and regression flows to improve design efficiency and consistency Perform Functional Evaluation, Performance Benchmarking and Deployment of New Tools Provide CAD Software & Linux User Support for CMOS Design Engineers & IC Layout Designers Prepare and maintain clear user documentation, best practices and training material for design teams across sites Responsible for diagnosis, resolution, regression of reported problems in a timely manner Interfacing directly with EDA Vendors’ Application and support teams to resolve and influence product improvements Support additional CAD-related initiatives and projects as assigned Qualifications & Requirements: BA/BS Degree in Electrical Engineering, Computer Science or related field Minimum 7 years of experience with analog and digital new product development CMOS IC CAD support using EDA tools Must have experience supporting: 1. Cadence Virtuoso Schematic Editor and Layout Suite, Spectre, Spectre-RF, Multi-Mode Simulator, Physical Layout tools, Assura, PVS, Pegasus, Innovus, Tempus 2. Siemens Analog Fast-Spice, Questa, Parasitic CALIBRE PVS, XRC 3. Synopsys Design Compiler, VCS, SpyGlass and other tools Programming languages: DFII SKILL, PERL, MATLAB, Tcl/Tk, C / C++, Python Proficient at Linux OS, utilities, and scripting Desired Characteristics & Attributes: Excellent written and verbal communication skills required Ability to work well with others in a fast-paced collaborative team environment Strong problem-solving skills, attention to detail and a proactive approach to continuous improvement. Compensation Range: At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. T he annual base salary range for this role is $164,800.00 – $226,600.00. The final offer is determined by factors such as location, experience, education, and training. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success. Benefits offered : 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans. SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program. Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. Innovation on Top – Philosophies of Innovation with Rajesh Vashist Fabrication Knowledge – An Interview with Rajesh Vashist SiTime Corporation – YouTube #LI-SITIME

Full job record

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TitlePrincipal Engineer, CAD
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CountryUnited States
RegionCA
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Salary Rawsalary range for this role is $164,800.00 – $226,600
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First Seen At2026-05-31 18:53:32Z
Last Seen At2026-06-20 14:28:20Z
Last Checked At2026-06-20 14:28:20Z
Last Changed At2026-06-20 14:28:20Z
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Source Posted At2026-04-28 17:10:00Z
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    "requisitionDescription": "<div><div><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;' data-pasted=\"true\"><strong><span style=\"font-size: 18px; font-family: arial, sans-serif;\">About SiTime</span></strong></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><br></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;' data-pasted=\"true\"><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">SiTime is the Precision Timing company.&nbsp;</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><p><span style=\"font-size: 18px; font-family: arial, sans-serif; color: black;\">Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit</span><span style=\"font-size: 18px; font-family: arial, sans-serif;\">&nbsp;<a href=\"https://www.globenewswire.com/Tracker?data=KZboO_E5KYNf2nXu9snYUrujcxPVV14r8VUqaw-krQjviK4SVzg-T3gX0Yv8pdrIU2yKG5VITW08WA-AWCTQKQ==\" target=\"_blank\" style=\"font-size: 18px;\">www.sitime.com</a>.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>Job Summary</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-size: 18px; font-family: arial, sans-serif;\">The&nbsp;</span><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>Principal Engineer, CAD</strong></span><span style=\"font-size: 18px; font-family: arial, sans-serif;\">&nbsp;will provide CAD Software support for Digital, Analog and Mixed-Signal designs, using Cadence, Synopsys, Siemens, Keysight &amp; 3<sup>rd</sup> party vendor tools. Responsibilities include user support for Behavioral, RTL and Analog Designs, Schematics, Analog Mixed-Signal Simulations, IC Physical Design layout, CAD tool customizations, Linux Support, implementation and testing of new software tools and deploy new CAD Tool flows. The Principal CAD Engineer will also interface with EDA Tool Vendors and have responsibilities for implementation and performance testing of new software releases, prior to deploying to IC Designers across multiple engineering sites.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>Responsibilities:</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Provide full lifecycle support for custom CAD flows, including tool development, installation, configuration, maintenance and upgrades across Cadence, Synopsys, Siemens and Keysight platforms</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Own PDK installation, validation, customization, maintenance and release management, ensuring alignment with foundry and keeping up to date versions always ready</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Support and maintain end-to-end tapeout flows, including coordinating and executing tapeout submissions to foundries, ensuring compliance with foundry requirements, schedules and quality standards</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Support Schematic Capture, Analog and Mixed-signal Simulation, Layout and Layout Verification software and workflows using established revision-controlled processes</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Support and maintain digital simulation, verification environments, digital place-and-route tools</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Develop and maintain CAD utilities, automation scripts and regression flows to improve design efficiency and consistency</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Perform Functional Evaluation, Performance Benchmarking and Deployment of New Tools</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Provide CAD Software &amp; Linux User Support for CMOS Design Engineers &amp; IC Layout Designers</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Prepare and maintain clear user documentation, best practices and training material for design teams across sites</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Responsible for diagnosis, resolution, regression of reported problems in a timely manner</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Interfacing directly with EDA Vendors&rsquo; Application and support teams to resolve and influence product improvements</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Support additional CAD-related initiatives and projects as assigned</li></ul><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-left:.5in;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>Qualifications &amp; Requirements:</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>&nbsp;</strong></span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">BA/BS Degree in Electrical Engineering, Computer Science or related field</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Minimum 7 years of experience with analog and digital new product development CMOS IC CAD support using EDA tools</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Must have experience supporting:<ul style=\"margin-bottom: 0in; list-style-type: circle; font-family: initial; font-size: initial;\"><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">1. Cadence Virtuoso Schematic Editor and Layout Suite, Spectre, Spectre-RF, Multi-Mode Simulator, Physical Layout tools, Assura, PVS, Pegasus, Innovus, Tempus</li><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">2. Siemens Analog Fast-Spice, Questa, Parasitic CALIBRE PVS, XRC</li><li style=\"margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 18px; font-family: arial, sans-serif;\">3. Synopsys Design Compiler, VCS, SpyGlass and other tools</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Programming languages: DFII SKILL, PERL, MATLAB, Tcl/Tk, C / C++, Python</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Proficient at Linux OS, utilities, and scripting</li></ul></li></ul><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>Desired Characteristics &amp; Attributes:</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Excellent written and verbal communication skills required</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Ability to work well with others in a fast-paced collaborative team environment</li><li style=\"margin: 0in; font-size: 18px; font-family: arial, sans-serif;\">Strong problem-solving skills, attention to detail and a proactive approach to continuous improvement.</li></ul><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;' data-pasted=\"true\"><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>Compensation Range:</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\">At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.&nbsp;</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><br></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;' data-pasted=\"true\"><span style='font-family:\"Arial\",sans-serif;'>T<span style=\"font-size: 18px;\">he annual base salary range for this role is $164,800.00 &ndash; $226,600.00. The final offer is determined by factors such as location, experience, education, and training.</span></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><br></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\">In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals&mdash;reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company&rsquo;s future growth and success.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>&nbsp;</strong></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong>Benefits offered</strong>: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><br></span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"font-family: arial, sans-serif; color: black; background: white; font-size: 18px;\">SiTime is an&nbsp;</span><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><a href=\"http://www.sitime.com/images/EEO-is-the-law.pdf\" target=\"_blank\" style=\"font-size: 18px;\"><span style=\"color: blue; background: white;\">Equal Opportunity Employer</span></a></span><span style=\"font-family: arial, sans-serif; color: black; background: white; font-size: 18px;\">. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.&nbsp;</span><span style=\"font-family: arial, sans-serif; font-size: 18px;\">SiTime participates in the <a href=\"http://www.sitime.com/images/E-Verify-Participation-Poster.pdf\" target=\"_blank\" style=\"font-size: 18px;\"><span style=\"color: blue;\">E-Verify</span></a> program.</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><strong><span style=\"color: black;\">Learn More about SiTime:&nbsp;</span></strong></span><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">Review the&nbsp;</span><span style=\"font-family: arial, sans-serif; font-size: 18px;\"><a href=\"https://www.sitime.com/company/careers\" target=\"_blank\" style=\"font-size: 18px;\">Get to Know SiTime</a></span><span style=\"font-family: arial, sans-serif; color: black; font-size: 18px;\">&nbsp;section of our career page to explore our culture, values, and what makes us unique.&nbsp;</span></p><ul style=\"margin-bottom:0in;margin-top:0in;\" type=\"disc\"><li style=\"margin: 0in 0in 11.25pt; font-size: 18px; font-family: arial, sans-serif; color: black; text-align: justify;\"><span style=\"color: windowtext;\"><a href=\"https://www.innovatorsontap.com/podcast/the-philosophy-of-innovation-w-rajesh-vashist\" target=\"_blank\" style=\"font-family: arial, sans-serif; font-size: 18px;\">Innovation on Top &ndash; Philosophies of Innovation with Rajesh Vashist</a></span></li><li style=\"margin: 0in 0in 11.25pt; font-size: 18px; font-family: arial, sans-serif; color: black; text-align: justify;\"><span style=\"color: windowtext;\"><a href=\"https://www.fabricatedknowledge.com/p/an-interview-with-rajesh-vashist-3e0#details\" target=\"_blank\" style=\"font-family: arial, sans-serif; font-size: 18px;\">Fabrication Knowledge &ndash; An Interview with Rajesh Vashist</a></span></li><li style=\"margin: 0in 0in 11.25pt; font-size: 18px; font-family: arial, sans-serif; color: black; text-align: justify;\"><span style=\"color: windowtext;\"><a href=\"https://www.youtube.com/user/sitimecorp/videos\" target=\"_blank\" style=\"font-family: arial, sans-serif; font-size: 18px;\">SiTime Corporation &ndash; YouTube</a></span></li></ul><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;margin-bottom:11.25pt;text-align:justify;'><span style=\"color: rgb(255, 255, 255); font-family: arial, sans-serif; font-size: 18px;\">#LI-SITIME</span></p><p style='margin:0in;font-size:16px;font-family:\"Times New Roman\",serif;'><em><span style=\"font-family: arial, sans-serif; font-size: 18px;\">&nbsp;</span></em></p></div></div>\n",
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