Home › Companies › Espace › FPGA Verification Engineer - Avionics

FPGA Verification Engineer - Avionics

Espace · Saratoga, CA · On Site · Active · $150,000–$250,000 / year · Lever

Job facts

Field	Value
Company	Espace
Title	FPGA Verification Engineer - Avionics
Normalized title	-
Department / team	E-Space US / Engineering & Operations
Location	Saratoga, CA, United States
Work model	On Site
Employment type	Full Time
Salary	$150,000–$250,000 / year
Status	active
ATS provider	Lever
Posted / first seen	2026-04-02 / 2026-05-29
Changed / last seen	2026-05-29 / 2026-06-06

Related slices

Page	What it contains	Open
Company jobs	Active postings from Espace.	Open
Company breakdowns	Role, location, ATS, and work model facets for this company.	Open
ATS provider jobs	Active postings observed through Lever.	Open
Provider filtered search	The same provider as a filtered job collection.	Open
City jobs	Active postings in Saratoga.	Open
Department jobs	Active postings in E-Space US.	Open
Work model jobs	Active On Site postings.	Open
Lifecycle events	Open, update, close, and reopen events for this posting.	Open
Original posting	Canonical source or apply URL captured from the ATS.	Open

Linked records

Company	Espace
Source	0e4c8640-c166-4c81-94c1-78a80cc89393
ATS provider	Lever

Description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are hiring FPGA Verification Engineers to build and maintain the verification infrastructure for satellite avionics FPGA designs. You will develop UVM-based testbenches, create coverage-driven verification plans, and ensure RTL correctness for flight-critical FPGA firmware across multiple subsystems. This role is instrumental in establishing a rigorous verification methodology for the program. Why E-Space is right for you: As a member of our team, you will play a crucial role in driving our success. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals. In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry. We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space: • An opportunity to really make a difference • Sustainability at our core • Fair and honest workplace • Innovative thinking is encouraged • Competitive salaries • Continuous learning and development • Health and wellness care options • Financial solutions for the future • Optional legal services (US only) • Paid holidays • Paid time off Key Responsibilities: Develop UVM-based verification environments including agents, scoreboards, and bit-accurate reference models. Create and maintain a reusable, extendable UVM framework supporting multiple FPGA targets and device configurations. Write verification plans derived from requirements specifications and architectural documents. Develop functional coverage models and drive coverage closure for all FPGA designs. Perform RTL simulation using industry-standard tools. Implement clock-domain crossing verification and timing/stability analysis. Apply lint and static-analysis tools to identify design issues early in the development cycle. Support hardware bring-up by creating tests that model and recreate hardware interactions in simulation. Document verification results, coverage metrics, and test plans with clear technical writing. Collaborate with FPGA designers and system engineers to refine requirements and close verification gaps. Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in FPGA or ASIC verification. Strong expertise in SystemVerilog and UVM-based verification methodology. Experience building UVM agents, environments, and generating constrained-random stimulus. Proficiency with at least one industry-standard RTL simulator. Understanding of functional coverage techniques and coverage-driven verification. Ability to read and understand PCB schematics and hardware interfaces for test development. Preferred Qualifications: Experience verifying designs for space, aerospace, or high-reliability applications. Familiarity with formal verification tools. Background in embedded software interaction with FPGA firmware. Experience with continuous integration workflows for verification regressions. Proficiency in Python, TCL, or shell scripting for test automation and infrastructure. Exposure to DFMEA and high-reliability digital design review processes. Tools & Technologies: Industry-standard RTL simulators (e.g., VCS, QuestaSim, or equivalent) UVM verification methodology Lint and CDC analysis tools Python/TCL scripting for automation

Full job record

Job ID	8e291eb66fefc074af8598652149c5f40e5ae6b0
Org ID	e990e975-83d3-4663-9e17-f465a630f542
Source ID	0e4c8640-c166-4c81-94c1-78a80cc89393
Board ID	0e4c8640-c166-4c81-94c1-78a80cc89393
Provider	lever
Provider Job Key	fa670d27-1dc5-4b10-81a6-9fb183275144
Title	FPGA Verification Engineer - Avionics
Normalized Title	—
Status	active
Active	yes
Location Text	Saratoga, CA
Department	E-Space US
Team	Engineering & Operations
Employment Type	Full-Time
Workplace Type	on_site
Remote Policy	—
Country	United States
Region	CA
City	Saratoga
Salary Raw	USD 150000-250000 per-year-salary
Salary Min	150,000
Salary Max	250,000
Salary Currency	USD
Salary Period	year
Source URL	https://jobs.lever.co/espace/fa670d27-1dc5-4b10-81a6-9fb183275144
Apply URL	https://jobs.lever.co/espace/fa670d27-1dc5-4b10-81a6-9fb183275144/apply
First Seen At	2026-05-29 07:07:40Z
Last Seen At	2026-06-06 19:12:13Z
Last Checked At	2026-06-06 19:12:13Z
Last Changed At	2026-05-29 07:07:40Z
Inactive At	—
Source Posted At	2026-04-02 22:46:04Z
Source Updated At	—
Raw Payload Uri	s3://job-postings-prod-raw-590183727216/raw/provider=lever/board=espace/date=2026-06-06/2026-06-06T19-12-11-686Z-efb9c8f38a20ecf78d9a90ab2968642b4db6ac83147e0e9af0d4e6ee8081f10b.json

Event Fields

{
  "content_hash": "0abaa808cab4bbcabdc82036811bf26a66760cd5b81cd2eedc24b27391f23f71",
  "source_hash": "fd54fe7393ac74ab5cb341ea55fd05485e62c7a25279059d7a1b7a89557d2161",
  "last_changed_at": "2026-05-29T07:07:40.070Z",
  "active_status": "active"
}

Parsed Structured

{
  "language": "en",
  "location": {
    "raw": "Saratoga, CA",
    "city": "Saratoga",
    "region": "CA",
    "country": "United States",
    "is_remote": false,
    "confidence": 0.9
  },
  "salary_max": 250000,
  "salary_min": 150000,
  "inferred_at": "2026-06-06T19:12:13.654Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en",
    "location": {
      "raw": "Saratoga, CA",
      "city": "Saratoga",
      "region": "CA",
      "country": "United States",
      "is_remote": false,
      "confidence": 0.9
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": "year",
  "workplace_type": "on_site",
  "salary_currency": "USD"
}

Extensions

{}

Native Structured

{
  "lists": [
    {
      "text": "Key Responsibilities:",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Develop UVM-based verification environments including agents, scoreboards, and bit-accurate reference models.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Create and maintain a reusable, extendable UVM framework supporting multiple FPGA targets and device configurations.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Write verification plans derived from requirements specifications and architectural documents.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Develop functional coverage models and drive coverage closure for all FPGA designs.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Perform RTL simulation using industry-standard tools.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Implement clock-domain crossing verification and timing/stability analysis.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Apply lint and static-analysis tools to identify design issues early in the development cycle.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Support hardware bring-up by creating tests that model and recreate hardware interactions in simulation.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Document verification results, coverage metrics, and test plans with clear technical writing.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Collaborate with FPGA designers and system engineers to refine requirements and close verification gaps.</li>\n</ul>"
    },
    {
      "text": "Required Qualifications:",
      "content": "\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">4+ years of experience in FPGA or ASIC verification.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Strong expertise in SystemVerilog and UVM-based verification methodology.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience building UVM agents, environments, and generating constrained-random stimulus.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Proficiency with at least one industry-standard RTL simulator.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Understanding of functional coverage techniques and coverage-driven verification.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Ability to read and understand PCB schematics and hardware interfaces for test development.</li>\n"
    },
    {
      "text": "Preferred Qualifications:",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience verifying designs for space, aerospace, or high-reliability applications.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Familiarity with formal verification tools.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Background in embedded software interaction with FPGA firmware.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with continuous integration workflows for verification regressions.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Proficiency in Python, TCL, or shell scripting for test automation and infrastructure.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Exposure to DFMEA and high-reliability digital design review processes.</li>\n</ul>"
    },
    {
      "text": "Tools & Technologies: ",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Industry-standard RTL simulators (e.g., VCS, QuestaSim, or equivalent)</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">UVM verification methodology</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Lint and CDC analysis tools</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Python/TCL scripting for automation</li>\n</ul>"
    }
  ],
  "country": "US",
  "createdAt": 1775169964418,
  "updatedAt": null,
  "categories": {
    "team": "Engineering & Operations",
    "location": "Saratoga, CA",
    "commitment": "Full-Time",
    "department": "E-Space US",
    "allLocations": [
      "Saratoga, CA"
    ]
  },
  "salaryRange": {
    "max": 250000,
    "min": 150000,
    "currency": "USD",
    "interval": "per-year-salary"
  },
  "workplaceType": "onsite"
}

Get this page with API

Rendered from the bluedoor Job Postings API. Reproduce it:

GET https://api.bluedoor.sh/job-postings/v1/jobs/8e291eb66fefc074af8598652149c5f40e5ae6b0?include=descriptionJSON

GET https://api.bluedoor.sh/job-postings/v1/orgs/e990e975-83d3-4663-9e17-f465a630f542JSON

GET https://api.bluedoor.sh/job-postings/v1/sources/0e4c8640-c166-4c81-94c1-78a80cc89393JSON

GET https://api.bluedoor.sh/job-postings/v1/jobs/8e291eb66fefc074af8598652149c5f40e5ae6b0/eventsJSON

Docs · Get an API key