Member of Technical Staff, TPU & AMD GPU Performance Engineering

Inferact's mission is to grow vLLM as the world's AI inference engine and accelerate AI progress by making inference cheaper and faster. Founded by the creators and core maintainers of vLLM, we sit at the intersection of models and hardware—a position that took years to build. About the Role We're looking for a TPU and AMD GPU performance engineer to make vLLM a first-class inference engine across non-NVIDIA accelerators. Frontier inference cannot be locked to one hardware stack. As AMD GPUs, TPUs, and other accelerators become increasingly important, vLLM needs backend paths that are fast, correct, benchmarked, and maintainable across heterogeneous hardware platforms. You'll build and optimize AMD GPU and TPU backends, kernels, compiler integrations, runtime paths, and benchmarking infrastructure. You'll work at the boundary of inference systems, kernels, compilers, and hardware architecture, improving paths such as attention, GEMM, sampling, KV-cache, communication-heavy operations, and model serving on non-NVIDIA hardware. Your work will directly impact how broadly and efficiently the world can run AI inference with vLLM. Skills and Qualifications Minimum qualifications: Bachelor's degree or equivalent experience in computer science, engineering, machine learning systems, hardware systems, compilers, or similar. Hands-on experience optimizing workloads on AMD GPUs, TPUs, or another non-NVIDIA accelerator stack. Experience with AMD ecosystem tools such as ROCm, HIP, Triton, CK, AITER, or equivalent GPU performance libraries and tooling. Experience with TPU, XLA, JAX, Pallas, or related compiler and runtime tooling for accelerator workloads. Ability to optimize ML inference paths such as attention, GEMM, sampling, KV-cache, fused kernels, backend runtimes, or communication-heavy operations. Strong performance profiling and benchmarking discipline, including tokens/second, latency, throughput, correctness parity, hardware counters, and reproducible measurement methodology. Ability to navigate immature tooling, incomplete documentation, backend-specific rough edges, and cross-platform performance differences without getting stuck. Preferred qualifications: Experience with vLLM, SGLang, TensorRT-LLM, ATOM, JAX-based serving framework, or other LLM inference systems. Deep understanding of inference architecture and serving tradeoffs, including batching, KV-cache, decoding, prefill/decode scheduling, and backend performance constraints. Experience with compiler technologies such as XLA, MLIR, LLVM, Triton, Pallas, or other compiler / kernel DSLs, including lowering, fusion, and backend code generation. Knowledge of quantization techniques such as MXFP8, MXFP4, mixed precision, or hardware-specific numeric formats, and the ability to reason about accuracy/performance tradeoffs. Experience with distributed inference performance, including communication, memory movement, hardware topology, and scale-out bottlenecks across multi-accelerator workloads. Open-source contributions to vLLM, JAX/XLA, ROCm, Triton, PyTorch, compiler projects, or related ML systems infrastructure. Bonus points if you have: Delivered measurable AMD GPU performance improvements on critical inference paths using ROCm, HIP, Triton, CK, AITER, or equivalent tools. Implemented or significantly improved TPU inference support using JAX, XLA, Pallas, or related compiler/runtime tooling. Built cross-platform benchmarking infrastructure for TPU, AMD GPU, or other non-NVIDIA accelerator targets. Implemented automated performance regression detection across representative models, architectures, workloads, or hardware backends. Collaborated with AMD, Google TPU ecosystem teams, accelerator vendors, or platform teams to ship backend optimizations or vendor-supported inference paths. Logistics Location: This role is based in San Francisco, California. Will consider remote in the US for exceptional candidates. Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $400,000 USD + equity. Visa sponsorship: We sponsor visas on a case-by-case basis. Benefits: Inferact offers generous health, dental, and vision benefits as well as 401(k) company match.

{
  "content_hash": "5d87296e4029aa4d7b915b29274c62ad37559c3af00165891a4b316a09650747",
  "source_hash": "fab893ce326efdd48de467cdd2804780b85dae8f19fd116ceead5a482c8564ee",
  "last_changed_at": "2026-06-18T10:28:24.631Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "San Francisco",
    "city": "San Francisco",
    "region": "CA",
    "country": "United States",
    "is_remote": false,
    "confidence": 0.75
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-19T09:44:34.849Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en",
    "location": {
      "raw": "San Francisco",
      "city": "San Francisco",
      "region": "CA",
      "country": "United States",
      "is_remote": false,
      "confidence": 0.75
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": null,
  "workplace_type": "on_site",
  "salary_currency": null
}

{}

{
  "id": "24ea1266-bc29-4838-9a61-8adc1d5bb2c6",
  "team": "Research & Engineering",
  "title": "Member of Technical Staff, TPU & AMD GPU Performance Engineering",
  "jobUrl": "https://jobs.ashbyhq.com/Inferact/24ea1266-bc29-4838-9a61-8adc1d5bb2c6",
  "address": null,
  "applyUrl": "https://jobs.ashbyhq.com/Inferact/24ea1266-bc29-4838-9a61-8adc1d5bb2c6/application",
  "isListed": true,
  "isRemote": false,
  "location": "San Francisco",
  "updatedAt": null,
  "apiVersion": "ashby-non-user-graphql-v1",
  "department": "Research & Engineering",
  "publishedAt": null,
  "workplaceType": "OnSite",
  "employmentType": "FullTime",
  "secondaryLocations": []
}