FPGA Design Engineer IND

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    "description": "<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">At <span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to <span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO) </span>of hardware systems — a critical barrier to scalable adoption.</span></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology </span>powers a <span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric </span>that is both <span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution <span style=\"font-weight: bold\">reduces power consumption significantly </span>while preserving <span style=\"font-weight: bold\">high bandwidth and ultra-low latency </span>— unlocking unprecedented efficiency for AI training and inference at scale.</span></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift </span>in how AI hardware is built for the future.</span></p>\n<p><br></p>\n<p><span style=\"color: rgb(34, 34, 34); font-family: Inter, sans-serif; font-size: 12pt\">We are actively seeking an <span style=\"font-weight: bold\">FPGA Design Engineer</span> based in Hyderabad, India.</span><br></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt; font-weight: bold\">Responsibility:</span></p>\n<ul></ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Will be a key member of a small FPGA team that will own prototyping of Kandou’s architectures in FPGA</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Will need to work independently with low day-to-day supervision and own FPGA projects</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Will work with Kandou’s architecture and system software teams on FPGA prototyping and participate in the entire lifecycle of project including support.</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Will participate in technical discussions with IP providers and be responsible for driving some of them.</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">‪<span style=\"font-weight: bold\">Skills:</span></span></p>\n<ul></ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Demonstrated RTL development skills of 5+ years, only 1 can be academic</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Proficiency in Verilog and C programming is expected. Proficiency in using Linux for lab testing is expected.</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Working exposure for SystemC and scripting (Python) is desired.</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Clear understanding and usage of AXI and related AMBA protocols to connect multiple logical blocks in an FPGA</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Demonstrated computer architecture understanding in at least one of processors, PCIe , ethernet or storage protocols</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">‪<span style=\"font-weight: bold\">Preferred Experience:</span></span></p>\n<ul></ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Must have shipping FPGA design in at least one of the following: compute accelerators, networking, storage, processor prototyping</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Must have micro-architected, designed &amp; shipped at least two key logic functions of high or medium complexity in an FPGA design</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Must have participated in lab bring up &amp; validation of shipping FPGAs in the lab and in deployed use</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Must be familiar with Xilinx development tool chain and Versal, Virtex FPGAs</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Preferred: Deep exposure to PCIe devices – protocol design &amp; lab work</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Preferred: Deep exposure to data path blocks (PCIe, Networking or storage) that involved embedded processors in the FPGA.</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt; font-weight: bold\">Education</span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">4 year Bachelor of Tech/Engineering/equivalent in Computer Science, Computer Engineering, Electronics or related field</span></li>\n</ul>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Master of Tech/Engineering/equivalent in Computer Science, Computer Engineering, Electronics or related field is a plus but not required.</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"color: rgb(29, 34, 40); font-family: Inter, sans-serif; font-size: 12pt\">If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !</span></p>\n<p><span style=\"color: rgb(29, 34, 40); font-family: Inter, sans-serif; font-size: 12pt\"><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><span style=\"color: rgb(34, 34, 34)\">Visit us at </span><a href=\"https://www.kandou.ai/\" target=\"_blank\" rel=\"noopener noreferrer\">www.kandou.ai</a><span style=\"color: rgb(34, 34, 34)\"> and </span><a href=\"https://www.linkedin.com/company/kandou-ai/posts?lipi=urn%3Ali%3Apage%3Acompanies_company_index%3Bd9883c75-e180-4084-9488-1a503e730cfe\" target=\"_blank\" rel=\"noopener noreferrer\">https://www.linkedin.com/company/kandou-ai/</a></span></p>",
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