Design Validation Test - Lead/Principal Engineer

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Role Summary We are seeking a hands‑on DVT Technical Lead (Individual Contributor) to own and drive the Design Validation Test (DVT) process end‑to‑end across complex electrical engineering boards and full systems. You will define validation strategy, build test plans and infrastructure, lead deep debug and root‑cause analysis (RCA), and drive closure through design changes and re‑test. The domain includes difficult power delivery technology, fast high‑speed I/O, and electro‑mechanical systems with thermal, optics, and high‑power constraints. People management is not required (mentoring is a plus). What You’ll Own 1) Board / Subassembly DVT (EE-heavy) Own DVT for complex PCBAs and subassemblies from first power‑on through design sign‑off. Power validation: power‑up/down sequencing, regulator/hotswap behavior, rail margining, DC IR drop, and AC noise/ripple characterization. Clock distribution validation and high‑speed I/O interface validation (e.g., Ethernet/PCIe-class links, board‑to‑board connectors and cabling). Low‑speed system management interface validation (e.g., I2C/SPI/USB) and debug of intermittent or systemic failures. Stress/environmental testing (extended runtime, temperature cycling) and characterization under margined conditions. 2) System-level DVT (integration + electro-mechanical) Own system integration validation planning and execution across representative configurations and operating envelopes. Drive readiness and execution across lab and chamber environments, including dependency management (test scripts, instrumentation, SW readiness, sample availability). Validate and debug system-level issues spanning electrical, mechanical, thermal, and optics interactions. Partner with reliability and manufacturing teams to ensure DVT coverage supports ramp readiness and reduces escapes. Key Responsibilities DVT Strategy, Plans, and Coverage Define a risk‑based DVT strategy spanning board/subassembly engineering validation through system integration validation. Author and maintain DVT plans, procedures, and reports with crisp pass/fail criteria and coverage rationale. Establish stage gates and readiness reviews for execution quality (fixtures, instrumentation, scripts, SW readiness). Hands-on Validation, Debug, and Closure Build and own benchtop and rack-level validation setups that are repeatable and automation‑friendly. Lead RCA for validation failures; drive corrective actions with design teams; verify fixes through re‑test and data review. Execute and interpret power integrity/stability measurements (voltage/current stability, droop, ripple/noise, IR drop) and close gaps to requirements. Validate high‑speed interconnect performance and margin; isolate failures across channel, connector/cable, PHY, and firmware/diagnostics layers. DVT Infrastructure, Automation, and Data Partner with diagnostics/software to improve DVT throughput via scripting, logging, and standardized test stages. Define required data capture and reporting standards to accelerate debug and support release gating. Drive continual improvements to test coverage, efficiency, and repeatability across builds. Cross-functional Technical Leadership Align EE/ME/FW/Diagnostics/Reliability/Manufacturing on priorities, schedules, and closure criteria. Influence design-for-testability improvements (debug visibility, margining hooks, instrumentation points, serviceability). Minimum Qualifications BS/MS in Electrical or Computer Engineering (or equivalent experience). 8–15+ years of hardware validation/DVT experience on complex board and system-level products. Demonstrated ownership of board bring‑up and DVT execution: test plan creation, instrumentation, debug, and closure. Strong background in power delivery validation and measurement (sequencing, margining, droop, ripple/noise, IR drop). Strong background in high‑speed I/O validation and debug (PCIe/Ethernet‑class links; channel and system-level troubleshooting). Proficiency with lab equipment: oscilloscopes, logic analyzers, power supplies/analyzers, DC electronic loads; VNAs/BERTs as applicable. Strong written and verbal communication; ability to present results and drive decisions with data. Preferred / Nice-to-Have Experience with rack-scale and/or liquid-cooled systems; validation in environmental chambers. Experience supporting compliance/safety/EMC efforts as part of DVT readiness. Python (or similar) for test automation and data analysis; experience integrating results into dashboards/CI workflows. Experience mentoring engineers/technicians as an informal technical leader. Success Measures DVT plans are complete, prioritized, and executable; coverage gaps are explicit and tracked to closure. Validation failures convert quickly into RCAs and verified fixes; DVT becomes repeatable and less “heroic.” Power delivery and high-speed I/O risks are discovered early and do not surprise late in system integration. Test automation/data capture improves cycle time and increases confidence in release gating. Location : Sunnyvale, California The base salary range for this position is $175,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications. Why Join Cerebras People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras: Build a breakthrough AI platform beyond the constraints of the GPU. Publish and open source their cutting-edge AI research. Work on one of the fastest AI supercomputers in the world. Enjoy job stability with startup vitality. Our simple, non-corporate work culture that respects individual beliefs. Read our blog: Five Reasons to Join Cerebras in 2026. Apply today and become part of the forefront of groundbreaking advancements in AI! Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them. This website or its third-party tools process personal data. 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