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FPGA Design Engineer II

HPR · Needham, MA · On Site · Active · $129,000–$166,000 / year · Greenhouse

Job facts

FieldValue
CompanyHPR
TitleFPGA Design Engineer II
Normalized title-
Department / teamEngineering
LocationNeedham, MA, United States
Work modelOn Site
Employment type-
Salary$129,000–$166,000 / year
Statusactive
ATS providerGreenhouse
Posted / first seen2026-06-15 / 2026-06-16
Changed / last seen2026-06-19 / 2026-06-22

Related slices

PageWhat it containsOpen
Company jobsActive postings from HPR.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Greenhouse.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Needham.Open
Department jobsActive postings in Engineering.Open
Work model jobsActive On Site postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyHPR
Sourcea18f7e01-4c00-47c9-910a-6f82463e26cd
ATS providerGreenhouse

Description

HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we’re searching for a forward-thinking FPGA Design Engineer to help us build the future of capital markets infrastructure. As an FPGA Design Engineer at HPR, you will: Design, develop, optimize, and maintain high-performance FPGA compute and networking systems used in electronic trading Own the RTL design process from specification and coding through synthesis and FPGA implementation Partner with design verification engineers to review and execute comprehensive test plans Lead and mentor junior engineers, promoting our culture of continuous learning and collaboration Contribute to improving our development processes, tools, and methodologies Required Qualifications BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related 3+ years of experience in digital logic design for FPGAs or ASICs Proficiency in SystemVerilog (preferred) or VHDL Deep understanding of computer architecture and digital design concepts Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi) Comfortable working in a Linux environment Strong problem solving, debugging, and communication skills Desired Qualifications Experience working with Xilinx and/or Altera FPGAs Familiarity with FPGA architecture and advanced design techniques, including optimizations for synthesis and timing closure In-depth knowledge of networking protocols (IP, TCP, UDP) Experience with high-speed interfaces (PCIe, Ethernet, and/or DDR) Familiarity with C programming and scripting in Python and/or Perl Compensation: In compliance with Massachusetts law, the anticipated annual base salary range for this position is $129,000 to $166,000. Please note that this range represents the expected base salary for this role at the time of posting. The final offer may vary based on factors such as the candidate's experience, skills, and qualifications. This range does not include other forms of compensation such as potential bonuses, equity, or benefits. This position requires being on-site at our office in Needham, MA full-time (5 days per week) HPR does not currently provide employment sponsorship Hyannis Port Research is an Equal Opportunity Employer and is committed to providing a workplace free from discrimination and harassment. All employment decisions are made without regard to any characteristic protected by applicable federal, state, or local law. We are committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process and during employment, consistent with applicable law. Applicants who require an accommodation to participate in the application or interview process or will require accommodation if hired should contact us via the "Connect With Us" button on our Careers page.

Full job record

Job ID84e4c4949859e51db47a4c009b16d6c9bcb3251a
Org IDe2d68300-1d41-4302-b9b2-e17a2b4d54d9
Source IDa18f7e01-4c00-47c9-910a-6f82463e26cd
Board IDa18f7e01-4c00-47c9-910a-6f82463e26cd
Providergreenhouse
Provider Job Key7771688003
TitleFPGA Design Engineer II
Normalized Title
Statusactive
Activeyes
Location TextNeedham, MA
DepartmentEngineering
Team
Employment Type
Workplace Typeon_site
Remote Policy
CountryUnited States
RegionMA
CityNeedham
Salary Rawsalary range for this position is $129,000 to $166,000. Please note that this range represents the expected base salary for this role a
Salary Min129,000
Salary Max166,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://job-boards.greenhouse.io/hyannisportresearch/jobs/7771688003
Apply URLhttps://job-boards.greenhouse.io/hyannisportresearch/jobs/7771688003
First Seen At2026-06-16 07:37:36Z
Last Seen At2026-06-22 07:42:43Z
Last Checked At2026-06-22 07:42:43Z
Last Changed At2026-06-19 07:36:41Z
Inactive At
Source Posted At2026-06-15 14:01:04Z
Source Updated At2026-06-18 19:10:33Z
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=greenhouse/board=hyannisportresearch/date=2026-06-22/2026-06-22T07-42-43-275Z-bed6828f1fab60f81a4976f9a9a1aa3a3465a14e0636cfd7eb510b8624142251.json
Event Fields
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  "source_hash": "eadb0deb91e25eff7b6600c2ba196f0f7e367fbbef3a1a21ee09a1c13fafdae0",
  "last_changed_at": "2026-06-19T07:36:41.278Z",
  "active_status": "active"
}
Parsed Structured
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  "salary_max": 166000,
  "salary_min": 129000,
  "inferred_at": "2026-06-22T07:42:43.364Z",
  "launch_scope": {
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  },
  "remote_policy": null,
  "salary_period": "year",
  "workplace_type": "on_site",
  "salary_currency": "USD"
}
Extensions
{}
Native Structured
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  "metadata": [],
  "updated_at": "2026-06-18T15:10:33-04:00",
  "departments": [
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      "child_ids": [],
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  "company_name": "HPR",
  "requisition_id": 5780630003,
  "first_published": "2026-06-15T10:01:04-04:00",
  "application_deadline": null
}
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