Characterization Engineer

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    "description": "<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">At <span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to <span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO) </span>of hardware systems — a critical barrier to scalable adoption.</span></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology </span>powers a <span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric </span>that is both <span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution <span style=\"font-weight: bold\">reduces power consumption significantly </span>while preserving <span style=\"font-weight: bold\">high bandwidth and ultra-low latency </span>— unlocking unprecedented efficiency for AI training and inference at scale.</span></p>\n<p><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift </span>in how AI hardware is built for the future. </span></p>\n<p><br></p>\n<p><br><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">We are actively seeking a <span style=\"font-weight: bold\">Characterization Engineer for our lab in Switzerland (Lausanne)</span></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Responsibility</span></span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Lead end-to-end characterization of high-speed SerDes operating at symbol rates above 20 Gbaud</span><br></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Perform jitter, eye-diagram, BER, and margin measurements across PVT</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Characterize full transmitter and receiver electrical parameters</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Perform S-parameter, TDR and insertion loss measurements</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Collaborate with IP architects, digital and analog design teams</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Documentation of test results and procedures</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Write and architect test scripts for automation in Python</span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Required Experience</span></span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Proven experience characterizing high-speed SerDes designs (&gt;20Baud) over PVT</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Proven knowledge in both TX and RX characteristics for high-speed designs</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Proven experience using high-speed oscilloscopes, VNAs, and Spectrum Analyzers above 30GHz</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Experience defining test plans and test procedures</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Experience with Python, or other object-oriented programming for test automation, data analysis and report generation</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Experience with PAM modulation or multi-tonal modulation schemes is a plus</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Minimum 5 years of relevant work experience</span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Required Competencies</span></span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Self-motivated, with a strong sense of ownership and responsibility</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Good communicator and team player, with experience working in cross-functional teams</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Strong interest and experience in characterizing high-speed analog circuits</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Solid understanding of: SI concepts, modulation schemes, TX and RX fundamentals</span><br></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Experience with Python or other object-oriented languages</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Experience using high-speed oscilloscopes, VNAs, and Spectrum Analyzers</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Ability to multitask in a high energy environment</span></li>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Schematic entry or PCB design is a plus</span></li>\n</ul>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><br></span></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">Required Education</span></span></p>\n<ul>\n<li><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Bachelor´s or Master´s degree in EE, CE, or equivalent work experience</span></li>\n</ul>\n<p><br><br></p>\n<p><span style=\"text-decoration: underline\"><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Profiles submitted by third-party recruitment agencies will not be taken into consideration.</span></span></p>",
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