FPGA engineer. Timing. Granada, Spain

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    "description": "<p><span style=\"font-weight: bold;\"><span style=\"font-family: Lato, sans-serif;\">We're looking for an FPGA Engineer to join our Technology Exploration Unit team in Granada, Spain.</span></span></p>\n<p><br></p>\n<p><span style=\"font-weight: bold;\"><span style=\"font-family: Lato, sans-serif;\">Our Technology:</span></span></p>\n<p><br></p>\n<p><span style=\"font-family: Lato, sans-serif;\">We are the world leader in Resilient Positioning, Navigation and Timing (R-PNT) solutions that improve the reliability, performance, and safety of critical applications, and high-risk operations, even in GPS/GNSS-denied environments. We provide virtually fail-safe GNSS and PNT solutions for military and commercial applications worldwide, and ultra-precise synchronization (sub-ns) and frequency distribution for applications requiring a high degree of reliability and precision through White Rabbit PTP.</span></p>\n<p><span style=\"font-family: Lato, sans-serif;\">In addition, Safran has great expertise in Time Sensitive Networking (TSN) through several projects in the framework of aerospace with ESA to provide deterministic communications with zero-packet loss. Overall, we deliver highly dependable solutions that always have high accuracy and robust timing at their core.</span></p>\n<p><br></p>\n<p><span style=\"font-weight: bold;\"><span style=\"font-family: Lato, sans-serif;\">The Position:</span></span></p>\n<p><br></p>\n<p><span style=\"font-family: Lato, sans-serif;\">As an assistant R&amp;D engineer, you will be a key member of our Technology Exploration Unit in Granada, Spain. You will be involved in research and development tasks in the areas of telecommunications and deterministic networking.</span></p>\n<p><br></p>\n<p><span style=\"font-weight: bold;\"><span style=\"font-family: Lato, sans-serif;\">What you’ll be doing:</span></span></p>\n<p><br></p>\n<ul>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">You will have responsibility for understanding requirements, developing innovative projects, planning new features, and ensuring that all developments are delivered according to specification.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">We are all about improvement, so you will be able to identify opportunities to improve product performance, efficiency, and design. </span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">You will use your critical thinking and problem-solving skills to ensure the highest quality for the results considering scheduling, budget, and effort constraints.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">You will work with the latest and greatest in Resilient PNT and deterministic technologies!</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">You will have effective, constant communication with other project partners and project managers all the way from the kick-offs to the stakeholder meetings.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">You will participate in internal meetings to build a comprehensive work plan, manage the budget and personnel effort for projects.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">You will write deliverables, dissemination material, assist in project-related communication activities, and attend workshops and other events.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">You will be developing the key firmware and FPGA elements of different prototypes for TSN networking. Validation of the design will be an important part of the position, and you will be expected to produce test benches, simulations, and experimental evaluation strategies to verify the prototypes.</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold;\"><span style=\"font-family: Lato, sans-serif;\">What you Bring to Safran:</span></span></p>\n<ul>\n<li><span style=\"color: #222222;\"> </span><span style=\"color: #222222; font-family: 'Lato',sans-serif;\">Master’s Degree in Telecommunications, Software Engineering, Computer Science, or related. </span></li>\n<li><span style=\"color: #222222;\"> </span><span style=\"color: #222222; font-family: 'Lato',sans-serif;\">Excellent written and dissemination skills in English (advanced Cambridge certificate or similar, at least similar speaking skills). </span></li>\n<li><span style=\"color: #222222;\"> </span><span style=\"font-family: Lato, sans-serif;\">General knowledge of software engineering and development, embedded Linux, and Linux kernel drivers.</span></li>\n<li><span style=\"color: #222222;\"> </span><span style=\"font-family: Lato, sans-serif;\">Passion, energy, and high motivation to participate in industrial R&amp;D projects and initiatives.</span></li>\n<li><span style=\"color: #222222;\"> </span><span style=\"font-family: Lato, sans-serif;\">Teamwork, organization skills, autonomous work, and project management.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Required experience in:</span>\n<ul>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Knowledge of Xilinx FPGA tools and platforms (Vivado, Vitis, HLS, …).</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">General understanding of embedded software development, debugging, FPGA logic design and verification.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">FPGA logic design (VHDL/Verilog, test bench implementation, debugging, timing closure, ...).</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Provable experience successfully implementing and debugging FPGA IP cores for different project requirements, such as network accelerators, image processing extensions, …</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Extensive experience in repositories and version control systems (Git, SVN, …).</span></li>\n</ul>\n</li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Desirable experience in: </span>\n<ul>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Knowledge of Ethernet networking, such as link layer protocols, Ethernet MAC, data switching, VLAN and 802.1Q standards.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Previous experience with other data interfaces, such as Aurora, GMII, SGMII, RGMII, RapidIO serialization, PHY modules, or the Xilinx GTx transceivers.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Prior knowledge of timing, synchronization, and frequency dissemination (PTP, NTP, SyncE, or othes).</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Previous experience in R&amp;D projects.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Knowledge of the Xilinx architecture and platforms, e.g., Zynq-7000, UltraScale, Zynq-MPSoC.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Knowledge of embedded Linux tools and build systems (e.g., Buildroot, Petalinux, …).</span></li>\n</ul>\n</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold;\"><span style=\"font-family: Lato, sans-serif;\">The keys of our offer: </span></span><span style=\"font-family: Lato, sans-serif;\"> </span></p>\n<ul>\n<li><span style=\"color: #222222;\"> </span><span style=\"color: #222222; font-family: 'Lato',sans-serif;\">Be part of a leading and expanding company.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Health insurance.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Flexible work schedule.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">International and dynamic work environment in Granada, Spain.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">High possibilities to grow inside the company.</span></li>\n<li><span> </span><span style=\"font-family: Lato, sans-serif;\">Professional Career Plan.</span></li>\n</ul>",
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