FPGA Design Engineer

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    "url": "https://xanadu.applytojob.com/apply/jobs/details/E9Mj2ANjYd?&",
    "heading": "FPGA Design Engineer",
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    "description_html": "<div class=\"job_description\">\n\t\t\t\t\t<h3 style=\"line-height:1.38;background-color:#ffffff;margin-bottom:11px;padding:0pt 0pt 8pt 0pt;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">About Xanadu:</span></span></span></span></span><br><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Xanadu&#8217;s mission is to build quantum computers that are useful and available to people everywhere.</span></span></span></span></span></span></span><br><br><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">At Xanadu, we are learners, innovators, researchers, collaborators and problem solvers. We are creating something that has never been built before. Few people in their life will be able to be a part of something like this, where if we are successful, the technologies we develop will solve some of the world&#8217;s most challenging problems, and literally change the world. And that is something to be excited about!</span></span></span></span></span></span></span></h3><p style=\"line-height:1.38;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Your role and responsibilities:</span></span></span></span></span></span></span></p><p style=\"line-height:1.38;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">As an FPGA design engineer at Xanadu you will be responsible for development of new and existing FPGA designs for modules we develop in house to control and operate our photonic quantum computer. </span></span></span></span></span></span></span></p><p style=\"line-height:1.38;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">These modules are used for phase stabilisation of optical fiber connections, control of electro-optic modulators, operation of optical homodyne measurements, photon-number resolving detectors, laser pulse sequencing, and quantum error correction, among other use cases. FPGA designs interface with various peripheral devices (such as ADCs, DACs, etc), other FPGAs, and servers.</span></span></span></span></span><br><br><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">You will work on the interface between classical compute and control infrastructure (such as GPUs and CPUs) and FPGAs to minimize latency and maximize data throughput, using interfaces such as PCIe, Infiniband, RoCE, or other high-bandwidth interfaces. You will work closely with physicists, engineers, and technicians in our labs to design and integrate these modules into our quantum computer systems. You will also provide support to the teams using these modules, debugging issues and implementing new features to increase the functionality and usability of new and existing designs.</span></span></span></span></span></span></span></p><h3 style=\"line-height:1.38;margin-top:21px;margin-bottom:5px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Basic qualifications and experience:</span></span></span></span></span></span></span></h3><ul><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Course, project or work experience writing RTL (Verilog or VHDL, SystemVerilog preferred)</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Course, project or work experience developing FPGA designs interfacing with CPU/GPU (examples here)</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Course, project or work experience bringing up an FPGA design from scratch</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience with validation and verification of designs</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience writing simulation testbenches</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Familiarity with Vivado or Quartus (Vivado preferred)</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Familiarity with Python</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Some experience with TCL</span></span></span></span></span></span></span></li></ul><h3 style=\"line-height:1.38;margin-top:21px;margin-bottom:5px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Preferred qualifications and experience:</span></span></span></span></span></span></span></h3><ul><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Knowledge of general data communication interfaces and protocols (SPI, I2C, JTAG, PCIe, JESD, UART, USB, TCP/IP, etc.)</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience with clocking architecture, timing constraints, low jitter applications</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience with Xilinx FPGAs (Series 7, Ultrascale+, Versal) would be an advantage</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Familiarity with source control, particularly git</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Familiar with control systems design/theory (PID loops, feedback theory)</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience with bitstream/firmware/bootloader deployment strategies</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Background in hands-on debug and verification experience in a lab environment</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience with writing C/C++ code for embedded microcontrollers</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience with electronic test and measurement equipment (oscilloscope, JTAG debugging (ILA/VIO))</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Proficiency in analog and digital circuits design (e.g. op-amp, ADC/DAC, power management, FPGA, SRAM/DDR, etc.)</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience in reading and understanding electrical schematics, technical drawings, datasheets, and written work instructions, in order to be able to meaningfully participate in schematic review meetings and obtain FPGA design requirements from these documents</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Familiarity with photonics and optical physics</span></span></span></span></span></span></span></li></ul><p style=\"line-height:1.38;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"background-color:#ffffff;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">This is for a new position. Your base salary will be determined based on your location, experience, and internal benchmarks. The base salary range is 100,000 - 140,000 CAD. You will also be eligible for equity and benefits.</span></span></span></span></span></span></span></span></p><p> </p>\n\n<p><span style=\"font-size:12px\"><span style=\"font-family:Arial,Helvetica,sans-serif\">Our values are important. They are fundamental and lay the foundation for culture at Xanadu. Learn more about our values <a href=\"https://www.xanadu.ai/values\">here</a>.</span></span></p>\n\n<p><span style=\"font-size:12px\"><span style=\"font-family:Arial,Helvetica,sans-serif\">We are an equal opportunity employer and encourage candidates of all backgrounds to apply. We are committed to building an inclusive, safe, and equitable culture and fostering an environment where our employees feel included, valued, and heard. We are committed to meeting the needs of all individuals and support a barrier-free workplace. Should you require accommodations at any point during the recruitment process please contact Recruiting at <a href=\"/cdn-cgi/l/email-protection#582a3d3b2a2d312c31363f7e7b6e6c63203936393c2d763931\">recruiting&#64;xanadu.ai</a>. </span></span></p>\n\n<p><span style=\"font-size:12px\"><span style=\"font-family:Arial,Helvetica,sans-serif\">Please be advised that we may use artificial intelligence (AI) tools to assist in the screening and assessment of applicants for this position. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.</span></span></p>",
    "description_text": "About Xanadu:\n Xanadu’s mission is to build quantum computers that are useful and available to people everywhere.\n At Xanadu, we are learners, innovators, researchers, collaborators and problem solvers. We are creating something that has never been built before. Few people in their life will be able to be a part of something like this, where if we are successful, the technologies we develop will solve some of the world’s most challenging problems, and literally change the world. And that is something to be excited about!\n Your role and responsibilities:\n As an FPGA design engineer at Xanadu you will be responsible for development of new and existing FPGA designs for modules we develop in house to control and operate our photonic quantum computer.\n These modules are used for phase stabilisation of optical fiber connections, control of electro-optic modulators, operation of optical homodyne measurements, photon-number resolving detectors, laser pulse sequencing, and quantum error correction, among other use cases. FPGA designs interface with various peripheral devices (such as ADCs, DACs, etc), other FPGAs, and servers.\n You will work on the interface between classical compute and control infrastructure (such as GPUs and CPUs) and FPGAs to minimize latency and maximize data throughput, using interfaces such as PCIe, Infiniband, RoCE, or other high-bandwidth interfaces. You will work closely with physicists, engineers, and technicians in our labs to design and integrate these modules into our quantum computer systems. You will also provide support to the teams using these modules, debugging issues and implementing new features to increase the functionality and usability of new and existing designs.\n Basic qualifications and experience:\n Course, project or work experience writing RTL (Verilog or VHDL, SystemVerilog preferred)\n Course, project or work experience developing FPGA designs interfacing with CPU/GPU (examples here)\n Course, project or work experience bringing up an FPGA design from scratch\n Experience with validation and verification of designs\n Experience writing simulation testbenches\n Familiarity with Vivado or Quartus (Vivado preferred)\n Familiarity with Python\n Some experience with TCL\n Preferred qualifications and experience:\n Knowledge of general data communication interfaces and protocols (SPI, I2C, JTAG, PCIe, JESD, UART, USB, TCP/IP, etc.)\n Experience with clocking architecture, timing constraints, low jitter applications\n Experience with Xilinx FPGAs (Series 7, Ultrascale+, Versal) would be an advantage\n Familiarity with source control, particularly git\n Familiar with control systems design/theory (PID loops, feedback theory)\n Experience with bitstream/firmware/bootloader deployment strategies\n Background in hands-on debug and verification experience in a lab environment\n Experience with writing C/C++ code for embedded microcontrollers\n Experience with electronic test and measurement equipment (oscilloscope, JTAG debugging (ILA/VIO))\n Proficiency in analog and digital circuits design (e.g. op-amp, ADC/DAC, power management, FPGA, SRAM/DDR, etc.)\n Experience in reading and understanding electrical schematics, technical drawings, datasheets, and written work instructions, in order to be able to meaningfully participate in schematic review meetings and obtain FPGA design requirements from these documents\n Familiarity with photonics and optical physics\n This is for a new position. Your base salary will be determined based on your location, experience, and internal benchmarks. The base salary range is 100,000 - 140,000 CAD. You will also be eligible for equity and benefits.\n Our values are important. They are fundamental and lay the foundation for culture at Xanadu. Learn more about our values here .\n We are an equal opportunity employer and encourage candidates of all backgrounds to apply. We are committed to building an inclusive, safe, and equitable culture and fostering an environment where our employees feel included, valued, and heard. We are committed to meeting the needs of all individuals and support a barrier-free workplace. Should you require accommodations at any point during the recruitment process please contact Recruiting at [email protected] .\n Please be advised that we may use artificial intelligence (AI) tools to assist in the screening and assessment of applicants for this position. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.",
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