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ASIC Chip Design Lead

Eridu · Saratoga, CA, United States · On Site · Active · $250,000–$280,000 / year · Rippling ATS

Job facts

FieldValue
CompanyEridu
TitleASIC Chip Design Lead
Normalized title-
Department / teamASIC Engineering
LocationSaratoga, CA, United States
Work modelOn Site
Employment typeFull Time
Salary$250,000–$280,000 / year
Statusactive
ATS providerRippling ATS
Posted / first seen2026-02-04 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

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Department jobsActive postings in ASIC Engineering.Open
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Linked records

CompanyEridu
Source2e3b3faf-1f18-443b-b03c-ab436c316a6b
ATS providerRippling ATS

Description

company About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability. The company’s solutions and value proposition have been widely validated by leading hyperscalers. Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems. Visit our website eridu.ai to learn more. role Position Overview We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams. This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment. Responsibilities Hands-on RTL Development Write, review, and debug production-quality RTL in Verilog/SystemVerilog Own RTL blocks end-to-end from specification through signoff Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels Perform detailed code reviews and set a high technical bar for RTL quality Micro-Architecture Specification Draft detailed micro-architecture specifications derived from architecture documents and feature requirements Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution Physical-Design–Aware Design & Timing Closure Work closely with Physical Design to improve synthesis and place-and-route timing. Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements Verification Collaboration & Debug Partner with Design Verification to debug functional and performance issues Review functional and code coverage and provide actionable feedback Own bugs from discovery through fix, validation, and closure Full-Chip Integration & Signoff Own full-chip RTL integration and block roll-up Run chip-level synthesis, define constraints, and close chip-level timing Deliver timing-clean netlists to Physical Design that meet performance targets Execution Discipline & Technical Leadership Drive block- and chip-level design checklists as execution quality gates Review checklist status with designers and proactively push closure of open items Continuously refine design methodologies, checklists, and flows based on silicon learnings Lead by technical authority and hands-on execution rather than coordination alone Qualifications Strong hands-on experience with RTL design and micro-architecture Proven experience with full-chip integration and timing closure Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff Deep understanding of synthesis, static timing analysis, and physical-design collaboration Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams Demonstrated ability to drive execution in ambiguous, fast-moving environments Nice to Have Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation Hands-on experience defining and refining SDC constraints and improving post-layout timing Knowledge of high-performance networking architectures and Ethernet-based systems Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols Experience with chiplet-based system design Why Join Us? At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. Notice to Recruiting Agencies Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

Full job record

Job ID71f2bdf523f97b2c702553677918e1e79519d0a0
Org IDd05d9cdc-fa71-444b-b57a-6140fe525606
Source ID2e3b3faf-1f18-443b-b03c-ab436c316a6b
Board ID2e3b3faf-1f18-443b-b03c-ab436c316a6b
Providerrippling
Provider Job Key46272dc8-40a4-46fa-a3b8-90f573b360b5
TitleASIC Chip Design Lead
Normalized Title—
Statusactive
Activeyes
Location TextSaratoga, CA, United States
DepartmentASIC Engineering
Team—
Employment Typefull_time
Workplace Typeon_site
Remote Policy—
CountryUnited States
RegionCA
CitySaratoga
Salary RawUSD 250000-280000 YEAR
Salary Min250,000
Salary Max280,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://ats.rippling.com/eridu-ai/jobs/46272dc8-40a4-46fa-a3b8-90f573b360b5
Apply URLhttps://ats.rippling.com/eridu-ai/jobs/46272dc8-40a4-46fa-a3b8-90f573b360b5
First Seen At2026-05-29 07:14:02Z
Last Seen At2026-06-06 19:44:35Z
Last Checked At2026-06-06 19:44:35Z
Last Changed At2026-06-06 19:44:35Z
Inactive At—
Source Posted At2026-02-04 00:15:58Z
Source Updated At—
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=rippling/board=eridu-ai/date=2026-06-06/2026-06-06T19-44-33-762Z-4b761a1811184974f9facfa7bb3d3a7e8696180848a08b199b5b79a934e7d18e.json
Event Fields
{
  "content_hash": "89098bb43779caa15b4c42c04a3744e56c9a29b9eb4f111581815e4241a7f062",
  "source_hash": "8ebc32b312317a3fb90acb002d8f1c288dc8a47218c6d945ed9d70dd162d5347",
  "last_changed_at": "2026-06-06T19:44:35.572Z",
  "active_status": "active"
}
Parsed Structured
{
  "language": "en-us",
  "location": {
    "raw": "Saratoga, CA, United States",
    "city": "Saratoga",
    "region": "CA",
    "country": "United States",
    "is_remote": false,
    "confidence": 0.98,
    "workplace_type": "on_site"
  },
  "salary_max": 280000,
  "salary_min": 250000,
  "inferred_at": "2026-06-06T19:44:35.537Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en-us",
    "location": {
      "raw": "Saratoga, CA, United States",
      "city": "Saratoga",
      "region": "CA",
      "country": "United States",
      "is_remote": false,
      "confidence": 0.98,
      "workplace_type": "on_site"
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": "year",
  "workplace_type": "on_site",
  "salary_currency": "USD"
}
Extensions
{}
Native Structured
{
  "list_job": {
    "id": "46272dc8-40a4-46fa-a3b8-90f573b360b5",
    "url": "https://ats.rippling.com/eridu-ai/jobs/46272dc8-40a4-46fa-a3b8-90f573b360b5",
    "name": "ASIC Chip Design Lead",
    "language": "en-US",
    "locations": [
      {
        "city": "Saratoga",
        "name": "Saratoga, CA",
        "state": "California",
        "country": "United States",
        "stateCode": "CA",
        "countryCode": "US",
        "workplaceType": "ON_SITE"
      }
    ],
    "department": {
      "name": "ASIC Engineering"
    }
  },
  "detail_job": {
    "url": "https://ats.rippling.com/eridu-ai/jobs/46272dc8-40a4-46fa-a3b8-90f573b360b5",
    "name": "ASIC Chip Design Lead",
    "uuid": "46272dc8-40a4-46fa-a3b8-90f573b360b5",
    "board": {
      "logo": {
        "url": "https://secured-assets.ripplingcdn.com/us1/ats/6602cd8c72e7d7408d83a88f/ats_public/4819dea78df74ec490ef4449133be866-sensitive.png?Expires=1780861474&Signature=V-K3K2jNau0eIKZKjOiWzvLak0vSWmVSC2r7L2sGUDRX1kqZwZ7ayKO8L39Z3SNR2Ibuq-GIc9mEN6vsGPJlqCoRdqxKRU8wq~hEGeg38fQznfg9HxmAx~1~3Nk-phNpU8SvMIaPDMuU6CVPnFH8thAhtuXfXW3gTumL7vZpMoLQ58EHFZ5pmzbSNQY7mwPI0TJBdYsav7ruAyJIGuhyieb2DdkYG6i~G8A9ePYyctGEUzpp7trO1yWAF1vHUQ1pSK69xRZNQJNflNWJkBkt2qOIA5StPRV74BV~xOUdTXY~1ahIt1~-O~-LxCau8WJ6hGKdGlTPOtLumRHoyMmrsw__&Key-Pair-Id=K2SM3GXN9F9XGM",
        "name": "Eridu_Full Logo.png",
        "type": "image/png"
      },
      "slug": "eridu-ai",
      "title": "Eridu Careers",
      "banner": {
        "url": null,
        "name": "",
        "type": ""
      },
      "boardURL": "https://ats.rippling.com/eridu-ai/jobs",
      "fontType": null,
      "subtitle": null,
      "boardType": "RIPPLING",
      "linkColor": "#000000",
      "buttonColor": "#000000",
      "legalNotice": null,
      "buttonTextColor": null,
      "noOpeningsMessage": null,
      "groupJobsByLocation": false,
      "showBoardLogoOnJobPost": true,
      "showCompanyInfoUnderJobPost": false
    },
    "createdOn": "2026-02-03T16:15:58.335000-08:00",
    "department": {
      "name": "ASIC Engineering",
      "base_department": "ASIC Engineering",
      "department_tree": [
        "ASIC Engineering"
      ]
    },
    "companyName": "Eridu",
    "description": {
      "role": "<meta><h3 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:21pt;font-weight:600;letter-spacing:0.25px;margin-top:14px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"color:windowtext;white-space:pre-wrap;\">Position Overview</strong></b></h3><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">We are seeking a </span><b><strong style=\"white-space:pre-wrap;\">hands-on ASIC Chip Design Lead</strong></b><span style=\"white-space:pre-wrap;\"> to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment.</span></p><h3 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:21pt;font-weight:600;letter-spacing:0.25px;margin-top:14px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"color:windowtext;white-space:pre-wrap;\">Responsibilities</strong></b></h3><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Hands-on RTL Development</span></h6><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Write, review, and debug production-quality RTL in Verilog/SystemVerilog</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Own RTL blocks end-to-end from specification through signoff</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Perform detailed code reviews and set a high technical bar for RTL quality</span></li></ul><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Micro-Architecture Specification</span></h6><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Draft detailed micro-architecture specifications derived from architecture documents and feature requirements</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution</span></li></ul><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Physical-Design–Aware Design &amp; Timing Closure</span></h6><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Work closely with Physical Design to improve synthesis and place-and-route timing.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Analyze synthesis and P&amp;R reports and proactively drive timing, area, and power improvements</span></li></ul><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Verification Collaboration &amp; Debug</span></h6><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Partner with Design Verification to debug functional and performance issues</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Review functional and code coverage and provide actionable feedback</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Own bugs from discovery through fix, validation, and closure</span></li></ul><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Full-Chip Integration &amp; Signoff</span></h6><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Own full-chip RTL integration and block roll-up</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Run chip-level synthesis, define constraints, and close chip-level timing</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Deliver timing-clean netlists to Physical Design that meet performance targets</span></li></ul><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><span style=\"color:windowtext;white-space:pre-wrap;\">Execution Discipline &amp; Technical Leadership</span></h6><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Drive block- and chip-level design checklists as execution quality gates</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Review checklist status with designers and proactively push closure of open items</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Continuously refine design methodologies, checklists, and flows based on silicon learnings</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Lead by technical authority and hands-on execution rather than coordination alone</span></li></ul><h3 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:21pt;font-weight:600;letter-spacing:0.25px;margin-top:14px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"color:windowtext;white-space:pre-wrap;\">Qualifications</strong></b></h3><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Strong hands-on experience with RTL design and micro-architecture</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Proven experience with full-chip integration and timing closure</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Deep understanding of synthesis, static timing analysis, and physical-design collaboration</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Demonstrated ability to drive execution in ambiguous, fast-moving environments</span></li></ul><h3 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:21pt;font-weight:600;letter-spacing:0.25px;margin-top:14px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"color:windowtext;white-space:pre-wrap;\">Nice to Have</strong></b></h3><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Hands-on experience defining and refining SDC constraints and improving post-layout timing</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Knowledge of high-performance networking architectures and Ethernet-based systems</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with chiplet-based system design</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><br></p><h5 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:10px;margin-bottom:4px;text-align:start;padding-left:0px;\"><b><strong style=\"color:black;font-size:18pt;white-space:pre-wrap;\">Why Join Us?&nbsp;</strong></b></h5><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Notice to Recruiting Agencies</strong></b></h6><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.</span></p>",
      "company": "<meta><h3 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:21pt;font-weight:600;letter-spacing:0.25px;margin-top:14px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"color:black;white-space:pre-wrap;\">About Eridu </strong></b></h3><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver </span><i><em style=\"font-size:11pt;white-space:pre-wrap;\">Faster AI</em></i><span style=\"font-size:11pt;white-space:pre-wrap;\">. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">The company’s solutions and value proposition have been widely validated by leading hyperscalers.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Visit our website </span><a href=\"http://eridu.ai\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(30,74,169);cursor:pointer;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">eridu.ai</span></a><span style=\"font-size:11pt;white-space:pre-wrap;\"> to learn more.</span></p>"
    },
    "workLocations": [
      "Saratoga, CA"
    ],
    "employmentType": {
      "id": "Salaried, full-time",
      "label": "SALARIED_FT"
    },
    "payRangeDetails": [
      {
        "currency": "USD",
        "isRemote": false,
        "location": "Saratoga, CA",
        "rangeEnd": 280000,
        "frequency": "YEAR",
        "rangeStart": 250000
      }
    ],
    "activeJobApplication": {
      "basicQuestions": [
        {
          "oid": "first_name",
          "title": "First name",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "last_name",
          "title": "Last name",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "email",
          "title": "Email",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "current_company",
          "title": "Current company",
          "required": false,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "phone_number",
          "title": "Phone number",
          "required": true,
          "fieldType": "PHONE_NUMBER"
        },
        {
          "oid": "location",
          "title": "Location (city only)",
          "required": true,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "linkedin_link",
          "title": "LinkedIn link",
          "required": false,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "website_link",
          "title": "Website link",
          "required": false,
          "fieldType": "SHORT_ANSWER"
        },
        {
          "oid": "resume",
          "title": "Resume",
          "required": true,
          "fieldType": "FILE"
        },
        {
          "oid": "cover_letter",
          "title": "Cover letter",
          "required": false,
          "fieldType": "FILE"
        }
      ],
      "customQuestions": {
        "fields": [
          {
            "oid": "first_name",
            "title": "First name",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "last_name",
            "title": "Last name",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "email",
            "title": "Email",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "current_company",
            "title": "Current company",
            "required": false,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "phone_number",
            "title": "Phone number",
            "required": true,
            "fieldData": {},
            "fieldType": "PHONE_NUMBER"
          },
          {
            "oid": "location",
            "title": "Location (city only)",
            "required": true,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "linkedin_link",
            "title": "LinkedIn link",
            "required": false,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "website_link",
            "title": "Website link",
            "required": false,
            "fieldData": {},
            "fieldType": "SHORT_ANSWER"
          },
          {
            "oid": "resume",
            "title": "Resume",
            "required": true,
            "fieldData": {},
            "fieldType": "FILE"
          },
          {
            "oid": "cover_letter",
            "title": "Cover letter",
            "required": false,
            "fieldData": {},
            "fieldType": "FILE"
          }
        ]
      },
      "additionalQuestions": null
    },
    "hasAIEvaluationsEnabled": true,
    "eeocQuestionnaireEnabled": true,
    "applicationConfirmationTemplate": "66170c04267c15f732be1cf5",
    "eeocQuestionnaireEnabledForJobPost": true
  },
  "detail_meta": {
    "url": "https://ats.rippling.com/api/v2/board/eridu-ai/jobs/46272dc8-40a4-46fa-a3b8-90f573b360b5",
    "http_status": 200,
    "content_type": "application/json",
    "response_bytes": 23980
  },
  "detail_errors": []
}
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