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Director, PD development and integration

Avicena Tech, Corp. · Sunnyvale, CA, United States · On Site · Active · Rippling ATS

Job facts

FieldValue
CompanyAvicena Tech, Corp.
TitleDirector, PD development and integration
Normalized title-
Department / teamPD
LocationSunnyvale, CA, United States
Work modelOn Site
Employment typeFull Time
Salary-
Statusactive
ATS providerRippling ATS
Posted / first seen2026-04-13 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

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Company jobsActive postings from Avicena Tech, Corp..Open
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City jobsActive postings in Sunnyvale.Open
Department jobsActive postings in PD.Open
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Linked records

CompanyAvicena Tech, Corp.
Source975aa5ec-8f41-46cf-b409-2232313db55e
ATS providerRippling ATS

Description

company Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products.  ( www.avicena.tech ) role About the role: We are seeking a highly skilled team member to lead the development and manufacturing transfer of high-speed silicon photodetectors (PDs) optimized for microLED-based multi-terabit-per-second communications. This role focuses on managing critical partnerships and processes to enable the successful development and transfer of photodetectors into high-volume manufacturing working with leading semiconductor fabrication partners. This position is based in Sunnyvale, California. This position starts with a single hire with a plan to grow the team as the company and product develops. This is an ideal opportunity for someone looking to develop into a senior engineering management position. Responsibilities: New PD Design Development: Lead the development of innovative PD designs optimized for our applications. Work with internal and external resources to design and simulate PD performance. Work with internal resources to characterize PDs. Foundry Partnership Management: Lead and manage the foundry partnership, including the transfer of new photodetector designs and oversee any necessary process modifications. Ensure alignment between Avicena’s technical and business requirements and the foundry partner’s capabilities. Wafer Testing Management: Oversee the development and implementation of wafer testing strategies, including identifying and managing external vendors for wafer-level testing. Leverage expertise to define and validate test methodologies. Final Test Development: Collaborate with vendors to set up and manage final test processes, ensuring robust performance validation of packaged devices. Qualification: Work with a multi-disciplinary team to establish qualification of Avicena’s manufacturing flows and ultimate qualification to industry standards. Qualifications: Educational Background: BS, MS, or PhD in Materials Science and Engineering, Electrical Engineering, or Applied Physics. Industry Experience: Proven experience managing foundry partnerships or foundry processes. Deep understanding of semiconductor device physics and characterization techniques (e.g., SIMS, XRD, SEM, TEM). Familiarity with semiconductor wafer fabrication processes, including photolithography, thin-film deposition, and etching. Experience with packaging technologies, including hybrid bonding and wafer stacking is a plus. Ability to manage outsourcing to high volume manufacturing partners. Testing Expertise: Ability to oversee high-speed optoelectronics testing, including wafer-level and final test processes. Project Management Skills: Excellent interpersonal and communication skills to collaborate with internal teams, manage external vendors, and present complex technical findings. Ability to manage timelines, overcome technical challenges, and drive solutions in a dynamic work environment.

Full job record

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Org IDc840fd90-50b5-48c0-b289-dffed50c1cc1
Source ID975aa5ec-8f41-46cf-b409-2232313db55e
Board ID975aa5ec-8f41-46cf-b409-2232313db55e
Providerrippling
Provider Job Keyce7b8369-8406-4dcb-a3f3-240689035345
TitleDirector, PD development and integration
Normalized Title—
Statusactive
Activeyes
Location TextSunnyvale, CA, United States
DepartmentPD
Team—
Employment Typefull_time
Workplace Typeon_site
Remote Policy—
CountryUnited States
RegionCA
CitySunnyvale
Salary Raw—
Salary Min—
Salary Max—
Salary Currency—
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Source URLhttps://ats.rippling.com/general/jobs/ce7b8369-8406-4dcb-a3f3-240689035345
Apply URLhttps://ats.rippling.com/general/jobs/ce7b8369-8406-4dcb-a3f3-240689035345
First Seen At2026-05-29 07:13:36Z
Last Seen At2026-06-06 08:45:46Z
Last Checked At2026-06-06 08:45:46Z
Last Changed At2026-06-06 08:45:46Z
Inactive At—
Source Posted At2026-04-13 18:36:59Z
Source Updated At—
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      "role": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">About the role:</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">We are&nbsp;seeking&nbsp;a highly skilled team member to lead the development and manufacturing transfer of high-speed silicon photodetectors (PDs)&nbsp;optimized&nbsp;for&nbsp;microLED-based multi-terabit-per-second communications. This role focuses on managing critical partnerships and processes to enable the successful development and transfer of photodetectors into high-volume manufacturing working with leading semiconductor fabrication partners. This position is based in Sunnyvale, California. This position starts with a single hire with a plan to grow the team as the company and product develops. This is an ideal opportunity for someone looking to develop into a senior engineering management position.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Responsibilities:</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">New PD Design</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;</span><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Development:</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">Lead the development of</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">innovative PD designs</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">optimized</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">for our applications. Work with internal and external</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">resources to design and simulate</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">PD performance. Work with internal resources to characterize</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">PDs.</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Foundry Partnership Management:</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">Lead and manage the foundry partnership, including the transfer of new photodetector designs and</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">oversee any necessary</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">process modifications. Ensure alignment between</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">Avicena’s</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">technical</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">and business</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">requirements and the foundry</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">partner’s</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">capabilities.</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Wafer Testing Management:</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">Oversee the development and implementation of wafer testing strategies, including</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">identifying</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">and managing external vendors for wafer-level testing. Leverage</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">expertise</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">to define and</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">validate</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">test methodologies.</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Final Test Development:</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">Collaborate with vendors to set up and manage final test processes, ensuring robust performance validation of packaged devices.</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Qualification:</strong></b><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">Work with a multi-disciplinary team to</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">establish</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">qualification</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">of</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">Avicena’s</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">manufacturing flows and ultimate</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">qualification</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">to industry standards.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Qualifications:</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Educational Background:</strong></b></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">BS, MS, or PhD in Materials Science and Engineering, Electrical Engineering, or Applied Physics.</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Industry Experience:</strong></b></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Proven experience managing foundry partnerships or foundry processes.</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Deep understanding of semiconductor device physics and characterization techniques (e.g., SIMS, XRD, SEM, TEM).</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Familiarity with semiconductor wafer fabrication processes, including photolithography, thin-film</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">deposition, and</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">etching.</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Experience with packaging technologies, including hybrid bonding and wafer</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">stacking</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">is a plus.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Ability to manage outsourcing to</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">high volume manufacturing</span><span style=\"white-space:pre-wrap;\">&nbsp;</span><span style=\"font-size:11pt;white-space:pre-wrap;\">partners.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Testing Expertise:</strong></b></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Ability to oversee high-speed optoelectronics testing, including wafer-level and final test processes.</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Project Management Skills:</strong></b></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Excellent interpersonal and communication skills to collaborate with internal teams, manage external vendors, and present complex technical findings.</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;list-style:none;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Ability to manage timelines, overcome technical challenges, and drive solutions in a dynamic work environment.</span></li></ul></li></ul>",
      "company": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Avicena</strong></b><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;is a privately held company developing&nbsp;microLED&nbsp;based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace.&nbsp;Avicena&nbsp;is headquartered in&nbsp;Sunnyvale, California with a development center in&nbsp;Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with&nbsp;a track record&nbsp;of delivering breakthrough products.  (</span><a href=\"http://www.avicena.tech/\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(30,74,169);cursor:pointer;\"><span style=\"white-space:pre-wrap;\">www.avicena.tech</span></a><span style=\"font-size:11pt;white-space:pre-wrap;\">) &nbsp;</span><span style=\"white-space:pre-wrap;\">&nbsp;</span></p>"
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