Senior Physical Design Engineer

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation team. In this role, you will be responsible for the physical implementation of complex digital SoC designs from netlist to GDSII, targeting advanced process nodes for 5G, IoT, and LEO satellite communications applications. You will work closely with front-end design, verification, and timing teams to deliver high-quality, performance-optimized silicon. This is a full time, exempt position, based out of our Saratoga office.  The target base pay for this position is $120,000 - $220,000 annually.  The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Why E-Space is right for you: As a member of our team, you will play a crucial role in driving our success.  Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals.  In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry. We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space: • An opportunity to really make a difference • Sustainability at our core • Fair and honest workplace • Innovative thinking is encouraged • Competitive salaries • Continuous learning and development • Health and wellness care options • Financial solutions for the future • Optional legal services (US only) • Paid holidays • Paid time off WHAT YOU WILL BE DOING: • Lead physical design implementation from floorplanning through GDSII sign-off for complex SoC blocks and full-chip designs • Perform floorplanning, power planning, placement, clock tree synthesis (CTS), and routing • Drive physical design closure meeting PPA (Power, Performance, Area) targets across all design corners • Collaborate with the STA team to analyze and resolve timing violations through ECO-driven optimization • Conduct and resolve physical verification (DRC, LVS, ERC) issues in partnership with the signoff team • Develop and maintain physical design scripts, flows, and automation in Tcl/Python • Work with foundry process design kits (PDKs) and ensure design rule compliance on advanced nodes • Support integration of hard macros, memory compilers, and analog IP into top-level designs • Analyze and optimize signal integrity, including crosstalk and noise effects • Contribute to physical design methodology development and mentor junior engineers WHAT YOU BRING TO THIS ROLE: • Minimum 8+ years of experience in physical design of complex digital ASICs or SoCs • Deep expertise in Cadence Innovus, with broad familiarity with other P&R tools such as Synopsys ICC2 • Strong experience in floorplanning, power planning, placement, CTS, and routing for multi-million gate designs • Deep knowledge of timing-driven physical design and working with STA engineers for timing closure • Experience with physical verification tools (Mentor Calibre, Synopsys ICV) and DRC/LVS debug • Proficiency in scripting (Tcl, Python) for flow development and automation • Solid understanding of low-power design techniques (clock gating, power domains, UPF/CPF) • Experience with advanced process nodes and associated PDK constraints • Strong problem-solving skills and attention to detail in a deadline-driven environment BONUS POINTS: • Experience with 7nm or sub-7nm process nodes • Exposure to custom digital or mixed-signal IC physical design • Familiarity with signal integrity analysis tools and methodology • Experience with hierarchical physical design flows for very large SoCs • Background in satellite, 5G, or IoT chip design

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